Design Engineer Training

SARITA UNIYAL

VLSI Design Engineer

J-***(A), SECTOR-9, VIJAY NAGAR GHAZIABAD, U.P

Email – ******.*****@*****.***

Contact No. - 971-***-****

EDUCATIONAL QUALIFICATIONS:

QUALIFICATION INSTITUTION BOARD / UNIVERSITY YEAR PERCENTAGE

IGDTUW, Delhi

M.TECH 80.33%

IGDTUW, Delhi 2013-2015

(formerly known as IGIT,

(Till 3rd Semester)

(VLSI Design) Delhi)

B.TECH Uttar Pradesh Technical

HIET, Ghaziabad 2008-2012 79.33%

(ECE) University, Lucknow

A.I.S.S.C.E. Andhra Education

C.B.S.E 2008 87.4%

(Class XII) Society, New Delhi

A.I.S.S.E. J.K.G. Senior

C.B.S.E 2006 88.6%

(Class X) Secondary School

TECHNICAL SKILLS:

TOOLS – XILINX ISE 9.2i, CADENCE (ORCAD PSPICE). TANNER EDA 14.1

HARDWARE DESCRIPTION LANGUAGES - VHDL, VERILOG, EMBEDDED C.

Proficient use of Internet, E-mail, MS-Office.

PERSONAL SKILLS:

Good command over my subjects.

Comprehensive problem solving abilities.

Tutoring Engineering Students since 3 years.

Willingness to learn, team facilitator, hard worker.

TECHNICAL WRITING (M.TECH):

1. Advantages of Cascode Current Mirrors over Simple Current Mirrors and improvement in voltage swing by appropriate

transistor dimensioning.

2. Improvement of Existing TRAFF circuit and simulation on ORCAD PSPICE resulting in simple topology, high input current

sensitivity and low response time.

PUBLICATIONS:

S. Uniyal, N. Mittal, Dr. Jasdeep Kaur “ High Bandwidth Voltage Amplifier using CCII+”,

IJETR (International Journal of Engineering and Technical Research) 2015.

PROJECT WORK:-

M.Tech

1. Adiabatic Logic based Power Efficient Multiplier design

Year: February 2015- present

Adiabatic Logics recovers energy dissipated as heat. They can be efficiently used in low power digital devices operating at low

frequencies like smart cards and sensors. Schematic Layout and Simulations will be done on Tanner EDA tool.

2. High bandwidth Current Conveyor II generation.

Year: 2014

A translinear loop based current conveyor II was implemented on PSPICE 16.6 version and a Voltage Amplifier was implemented

using CCII.

B.Tech

1. Automated coal mining using Microcontroller 8051

Year: 2011

2. Two Tank Overflow Control System using PLC-SCADA.

Year: 2010

TRAINING / CERTIFICATIONS:-

Workshop - ASIC and CIC flow on CADENCE TOOLS, organised by IEEE Women in Engineering .

Training in AVR, 8051, PIC Microcontroller from CETPA INSTITUTE, NOIDA in 2012.

Training in PLC-SCADA from DIAC INSTITUTE, NOIDA in 2010.

1 month Summer Training in Prasar Bharti, New Delhi in 2011.

AWARDS AND ACHIEVEMENTS:

Qualified GATE 2014.

Qualified GATE 2012 and got 96.67 percentile among more than 2 lakh candidates.

Achieved Rank 1 out of 120 candidates for first and last year of B.Tech. Recipient of monetary award as well.

Secured third position in “BHARAT KO JAANO” written test conducted by RSS, under Vijay Nagar Zone.

Winner of inter-collegiate sport events for relay race and kho-kho.

Winner of inter-school dancing competitions.

EXTRA CURRICULAR:

Participated in School level Maths and Science Olympiads.

Participated in 5th National IT Aptitude Test held by NIIT and secured a rank of 16000 out of more than 75000 candidates.

Participated in various Dance Competitions.

PERSONAL PROFILE:

14th February, 1990

Date of Birth:

Father’s Name: Sri Jagdish Prasad Uniyal

Languages Known: English, Hindi

Hobbies: Listening to music, reading and travelling.

DECLARATION:

I hereby declare that the above mentioned information is correct to the best of my knowledge and I bear the responsibility for the

correctness of the above mentioned particulars.

Ghaziabad SARITA UNIYAL

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