Engineer Development
Resume:
Naveen Kumar
ASIC Verification Engineer
Email:- ******.******@*****.***
Contact: - +91-814*******
PROFESSIONAL SUMMARY
. 3+ years Experience in using Industry Standard EDA Tools for Front-End
Verification.
. Adept at verifying ASICs using SystemVerilog as well as in Coverage
Driven verification methodology.
. Experience in developing a thorough test plan, Strong ability to
analyze specifications to identify the test scenarios needed to achieve
functional testing and coverage goals.
. Expert in creating object-oriented, self-checking, reusable test
benches for block-level testing and full-chip simulation with
constrained-random stimulus and coverage analysis.
. Protocols worked on AMBA AXI3/AXI4/ACE/AXI5(CHI),
ETHERNET(1/10/40/100gbps) and SPI.
. Quick at finding, debugging, and analyzing the bugs/failures in RTL and
fixing them.
. Fluency with Verilog, SystemVerilog languages and OVM/UVM
methodologies.
. Several project cycles from concept through complete release.
. Possess Sound Analytical, Quantitative Research and Problem-
Solving Skills with rich experience in Verification
Methodologies.
WORK EXPERIENCE (PerfectVIPs and Maven Silicon Softech Pvt Ltd.)
March 2012 to present, PerfectVIPs Technology, Bangalore
Sept 2011-Jan 2012, Maven Silicon Softech Pvt Ltd., Bangalore
Project: AMBA AXI3/AXI4/ACE/AXI5(CHI) (Duration: Nov 2013 - Present) at
Synopsys India Pvt Ltd
Responsibilities:
. Study of AMBA AXI3/AXI4/ACE/CHI Protocol Specification
. Development of the Test plan to verify Interconnect for AXI3/AXI4
. Development of Test cases for AXI3/AXI4 Interconnect
. Development of the Test plan to verify Interconnect for ACE
. Development of Test cases for ACE Interconnect
. Development of the Test plan to verify CHI
. Development of Test cases for CHI
. Development of HVP(High Verification Planner) for AXI3/AXI4/CHI
. Identification and fixing of coverage holes
. Debug and fixing test cases
Project: Ethernet RS-FEC Verification Environment Development using UVM as
Verification Engineer at PerfectVIPs (Duration: May 2012 - Oct 2013)
Responsibilities:
. Study of Ethernet clause 91 IEEE P802.3bj specification
. Development of the RS-FEC Test plan from the Spec
. Implemented the 64B/66B to 256B/257B and 256B/257B to 64B/66B
Trancoder
. Development of Reed-solomon Encoder
. Implemented the Synchronization state machine/ FEC alignment state
machine in UVM Testbench Environment
. Development of alignment marker mapping and insertion
. Identification of Constrained Random scenarios and functional coverage
groups/points/bins
Project: Ethernet 1G PCS Verification Environment Development using UVM as
Verification Engineer at PerfectVIPs (Duration: May 2012 - Oct 2013)
Responsibilities:
. Study of Ethernet clause 36 IEEE 802.3 Section 3 specification
. Development of Transmit/Receive/Auto-Negotiation/Synchronization State
Machines in UVM methodology
. Developed the 1G PCS Transmitter and Receiver in UVM methodology
. Development of PMA Transmit and Receive in the 1G PCS for SGMII
interface
. Identification of Constrained Random scenarios and functional coverage
groups/points/bins
Project: Ethernet SGMII interface Verification Environment Development
using UVM as Verification Engineer at PerfectVIPs (Duration: May 2012 -
Oct 2013)
Responsibilities:
. Study of SGMII interface specification.
. Development of parallel to serial and serial to parallel serdes in UVM
methodology
. Testing of this serdes by connecting it with 1 G PCS 10 bit interface.
. Development of combined environment of 1G PCS and SGMII as per customer
requirement.
. Identification of Constrained Random scenarios and functional coverage
groups/points/bins
. Development of sequences & tests for SGMII
Project: Ethernet (1/10/40/100G) Verification using UVM as Verification
Engineer at PerfectVIPs (Duration: May 2012 - Oct 2013)
Responsibilities:
. Study of Ethernet IEEE 802.3 specification
. Development of the 1/10/40/100G Test plan from the Spec
. Debugging of 40 and 100G-BASER PCS transmit and receive process.
. Development of error scenario for 64/66 Encode-Decode, Scrambler,Block
Distribution,Alignment insertion,etc.
. Implementation of error injection knobs for 40/100G-BASER PCS.
. Development of tests and sequences.
. Verifying 40/100g with back-to-back connection
. Identification of Constrained Random scenarios and functional
coverage groups/points/bins
. Involved in documenting for protocol checkers and Monitor messages
. Developed and tested various connection of Ethernet Interfaces as per
the customer requirement
. Developed the Coverage for Ethernet interfaces like
XGMII/XAUI/GMII/MII/RMII/SGMII and for auto negotiation.
Project: Ethernet 10G MAC Verification Environment Development using UVM as
Verification Engineer at PerfectVIPs (Duration: May 2012 - Oct 2013)
Responsibilities:
. Study of Ethernet MAC L2 specification
. Development of the L2 Test plan from the Spec
. Developed the MAC TX/RX Engine in UVM methodology
. Implemented the packet generator for L2 packet generator in UVM
methodology
. Identification of Constrained Random scenarios and functional coverage
groups/points/bins
. Involved in documenting for protocol checkers and Monitor messages
. Development of sequences & tests for MAC
Project: SPI Verification Environment Development using UVM as Verification
Engineer at PerfectVIPs (Duration: March 2012 - April 2012)
Responsibilities:
. Study of SPI specification (M68HC11 section 8)
. Development of Testplan
. Development of uvm environment for SPI Master & Slave
. Knob and Api implementation
. Implementation of verbosity & messaging in master & slave bfm
. Development of Testcases
EDUCATION
Maven Silicon Certified Advanced VLSI Design and Verification course
Institute: Maven Silicon VLSI Design and Training Center, Bangalore
Year: 2011-2012
Bachelor of Engineering: Shri Shankaracharya College Of Engineering &
Technology (CHHATTISGARH SWAMI VIVEKANANDA TECHNICAL UNIVERSITY), Bhilai,
C.G, India.
Discipline: Electronics & Telecommunication
CGPA: 7.62
Year: July 2011
H.S.C: Bokaro Ispat Sr. Sec. School, Bokaro, Jharkhand, India.
Board: CBSE
Discipline: Science
Year: June, 2006
Percentage: 81.5%
S.S.C: Bokaro Ispat Vidyalaya, Bokaro, Jharkhand, India.
Board: CBSE
Percentage: 83.83%
Year: June, 2004
TECHNICAL SKILLS
Knowledge RTL Coding, FSM based Design, Simulation, Code Coverage, and
Functional Coverage
HDL Verilog,
HVL SystemVerilog, OVM/UVM
EDA Tool Modelsim, NCSIM, QUESTASIM, VCS
Domain ASIC verification
PERSONAL DETAILS
DOB 18-11-1987
Contact Address #34/2A,Keerthana Appartment, Govinda
Sheety Palya,Electronic City Phase-
2,Bangalore-560100
Languages known English,Hindi
DECLARATION
I hereby declare that the above information is true to the best of
my knowledge and belief.
Place: Bangalore
Date:
Naveen Kumar
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