Manager Project
Resume:
Koyyada Dinesh Kumar
Email:**********@*****.***
Mobile:+91-810*******
SUMMARY
* 1 year of experience in electronic instruments testing and production
with distinction in B.Tech(ECE)
* Undergoing training of VLSI DESIGN and VERIFICATION.
* Expert in writing synthesizable RTL design codes using verilog.
* Good knowledge in developing verification Environment using system
verilog.
* Strong fundamentals in Digital Electronics.
* Expert in debugging and Simulation Issues.
* Good Exposure to Simulation with Questasim tool.
* Knowledge in Code Coverage & Functional Coverage.
* Excellent communication, debugging skills and a strong team player.
TECHNICAL SKILLS
Technical Skills Digital electronics,verilog,system verilog
Protocols AMBA-AXI
HDL Simulation Questasim
Tools
Coverage Code coverage and functional coverage
Synthesis Tools Xilinx ISE
PROFESSIONAL EXPERIENCE & PROJECTS
Company: MCIH CHENNAI
Position: PRODUCTION ENGINEER
Duration:
July 2013 to
July 2014
Description: Worked on production of electronic instruments like alarm
modules,calibrators,load cell indicators and totalisers.
Responsibility:
* To schedule the production of instruments for every week.
* To check the instruments given by R&D department and submit the report
to manager.
* To configure and check the electronic instruments.
* Investigate problems, analyze root causes and derive resolutions.
* To report the flaws and bugs in the instruments to manager.
PROJECT 1:
Company: ACUMMENS TECH
Duration:
December 2014 to
February 2015
Position: Trainee
TITLE: Dual Port RAM design and Verification Responsibilities
Description: Designed a DUAL PORT RAM using VERILOG and created a
Verification Environment from scratch using SYSTEM VERILOG.
Responsibility:
* Wrote verilog code for DUAL PORT RAM.
* Achieved 100% functional coverage.
* Created class based verification environment.
PROJECT 2:
Company: ACUMMENS TECH
Duration:
December 2014 to
February 2015
Position: Trainee
TITLE: Developing AMBA-AXI protocol Verification Environment
Description: Creating a class based Verification Environment for AMBA_AXI
Protocol BFM's.
Responsibility:
* Understanding the Behavior of AXI Protocol.
* Developing the Master and Slave BFM's.
* Developing the test scenarios.
* Developing the verification components using system verilog
EDUCATION
* Successfully completed 2 months VLSI front end training in design and
verification from ACUMMENS TECH.
* Completed a 1 month course in CDAC HYDERABAD in digital electronics
and verilog basics.
* Completed B.Tech from SCITS karimnagar,affiliated to JNTU HYDERABAD
with 85.8% in 2013.
* Completed Intermediate from narayana college with 74.4% in 2009.
* Completed SSC from Trinity college with 88.18% in 2007.
ACADEMIC PROJECTS
B.Tech Project: A DCT Approximation For Image Compression(IMAGE
PROCESSING)
Description:
* Here we compress the image by using DCT technique.
* This transformation matrix contains only zeros and ones.
* Given an image and image quality constraint (in terms of PSNR), we
determine the operand bit-width for each DCT coefficient such that DCT
computation energy is minimized.
Role: Created Problem Statement and Coding for DCT and IDCT blocks in Image
Compression.
ACHIEVEMENTS
* Stood top in my B.Tech 1st year result with 92.5%,and 26 rank in my
University(JNTU HYDERABAD).
* Qualified in national level fellowship ie CSIR UGC NET JRF with a rank of
319 in April 2013.
* Qualified in GATE with 75.73% and 277 score in 2014.
Seminars/workshops
* Certified in pcb layout.
* Certified in Technophillia robotic work shop.
* Certified in KL UNIVERSITY 4 DAY robotic work shop.
Personal profile
Name : DINESH
Father's name : Pochaiah
D.O.B : 21-09-1990
Nationality : Indian
Languages : English,Hindi,Telugu.
Hobbies : Reading books, listening music, Playing
cricket .
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