Design Designer

David Sherwin **** Bridford Lake Circle, Apt. L

Greensboro, NC 27407

919-***-****

**********@*****.***

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Profile

~ IC Layout Designer~

"17 years of proven experience developing new products in the Semiconductor

Industry"

Solution-oriented, analytical professional with extensive experience

delivering high-quality assignments as a contributing project team member.

Outstanding problem-solving and decision-making skills with a reputation

for being able to conceptualize solutions to challenging situations and

implementing practical, quality project plans. Areas of expertise encompass

the following:

> Full Custom Digital, Analog, and Mixed Signal Layout Design including

artwork extraction and Wirelist Compare verification, DRC, and production

based backend checks

> Cell library development, microprocessor core, cache, pad ring, and

datapath designs, including unit level floorplanning

> Tool experience includes: Maestro, Tanner, GeneSys (in-house, similar to

Cadence), UE2, Cadence Virtuoso XL, Hercules, Calibre LVS / DRC, LVI, and

Hilex Wirelist Compare

> Daily chip wide DRC rollup for tapeout of EV7 Alpha processor

> Individual and Box Lead experience; mentored and directed junior mask

designers

> Wrote a comprehensive design rule document for MEMS process

~ Key Achievement~

> Served as an integral member of Design Team for EV7 64-bit processor used

in the Human Genome Decoding project which was completed more than a year

ahead of schedule

> Served on the Tukwila Design Team, the first Two Billion Transistor

Microprocessor

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Professional Experience

RF MICRO DEVICES, Greensboro, NC, June 2014 - Dec 2014

Mask Designer (Contract)

. Completed clean, electrically sound layout edits to existing wireless

switches and created full custom layout for new switches.

IC-ENABLE, Dallas, TX, July 2013 - Oct 2013

Mask Designer (Contract)

. Custom digital and analog layout design in Samsung .14 nm FinFet process

PIXTRONIX - Qualcomm Company, North Andover, MA, Apr 2012 - Aug 2012

MEMS Mask Designer (Contract)

. Demonstrated technical expertise while completing layout of digital

shutters for video displays and resolution test patterns for optics

testing

INTEGRATED DEVICE TECHNOLOGY, Duluth, GA, Sept 2011 - Feb 2012

Mask Designer (Contract)

. Developed complete custom analog and mixed signal layout of the Bandgap

and PII schematics in .40 nm TSMC process

QUALCOMM, INC, Raleigh, NC, 2007 - 2009

Mask Designer (Contract)

. Created complete custom layout of caches, register file, and datapath

schematics in Scorpion (core) / Raptor Processor in .45 nm technology

. Redesigned the core in and ultra-high performance process

INTEL COMPUTER CORPORATION (Microprocessor Design Center, Hudson, MA, 2003

- 2006

Senior Mask Designer - Itanium Design Group

. Successfully completed numerous projects from inception to completion,

including Itanium 64-bit processors in .90 nm and .65 nm

DIGITAL / COMPAQ, Shrewsbury, MA, 1997 - 2003

Senior Mask Designer / Mask Designer - Alpha Development Group

. Consistently met timelines while completing numerous projects, including

EV6 (.35 bulk CMOS), EV67 (.25 bulk CMOS), EV68a (aluminum .18 bulk CMOS

Samsung), EV7 (.18 bulk CMOS IBM), and EV79 (.13 bulk CMOS)

~ Prior Experience~

DIGITAL EQUIPMENT CORPORATION, Hudson, MA, Jun 1997 - Oct 1997

Mask Design Co-op

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Education

QUINSIGAMOND COMMUNITY COLLEGE, Worcester, MA, 1996 - 1997

. Electronics, Microprocessors, and Digital Logic

. Dean's List Both Semesters - Selected for Layout Co-op with Digital

Equipment Corporation

UNIVERSITY OF MASSACHUSETTS, Amherst, MA, 1989-1992

. History, English, and Psychology

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