Engineering Design

CURRICULUM VITAE

N.ARUNKUMAR

****/**,

Mugappair East

Chennai- 600037.

Contact No: 770-***-****

Mail Id:********@*****.***

*************@*****.***

Career Profile

Objective

Seeking a challenging environment that encourages creativity and innovative

ideas that stimulates personal and professional growth.

PROFESSIONAL EXPERIENCE

1. ORGANISATION : VELTECH MULTITECH ENGINEERING

COLLEGE

DESIGNATION : ASSISTANT PROFESSOR

DEPARTMENT : ECE

DURATION : June 16TH 2011 to March 25th2015

2. ORGANISATION : S.A.ENGINEERING COLLEGE

DESIGNATION : LECTURER

DEPARTMENT : EEE

DURATION : June 21nd 2010 to May 31st 2011

3. ORGANISATION : PMR INSTITUTE OF TECHNOLOGY

DESIGNATION : LECTURER

DEPARTMENT : ECE

DURATION : July 10th 2009 to May 12th 2010

RESPONSIBILITIES:

. Scheduling and lecturing undergraduate and post graduate level

students on the subjects related to Electronics and Communication

Engineering such as Digital Electronics, VLSI Design, ADSD and VLSI

Architecture.

. Conducted Value Added courses using Cadence Virtuoso and Encounter

tool for undergraduate and graduate level students apart from their

regular University Curriculum for helping them to improve their

technical knowledge and skills.

. Supervising both undergraduate and post graduate (Masters) students in

their project work by investigating recent research based on the

student's area of interest; guiding and helping them to identify a

research topic, determining the appropriate research methodologies and

implementing the same using advanced tools like Cadence, H-spice,

Xilinx.

INDUSTRIAL WORK EXPERIENCE

. COMPANY NAME : Stromtek automation

. DESIGNATION : Systems Engineer.

. RESPONSIBILITIES : Had developed Electronic Controller,

Assembling and testing for process control

application

. DURATION : November 14th 2005 to January 31st,

2007.

Academics

. M.Tech (VLSI Design) 8.27 CPGA (REGULAR) Sathyabama University,

Chennai (2009).

. B.E.(Electrical and Electronics Engineering) 64% Arulmigu Kalasalingam

College of Engineering, Krishnan kovil.( Anna University )(2005)

. HSC 81.5% N.S.V.V.HSS Pattiveeranpatti(2001).

. SSLC 86.6% N.S.V.V.HSS Pattiveeranpatti(1999).

Technical Skills

HDL :VHDL, VERILOG

SIMULATION SOFTWARES :PSPICE, HSPICE,T-SPICE

HARDWARE DEVELOPMENT BOARDS :ALTERA AND XILINX FPGA BOARDS

EDA TOOLS :XILINX ISE, ALTERA QUARTUS II,

:CADENCE (NCSIM, VIRTUOSO

SCHEMATIC COMPOSER, LAYOUT

EDITOR,ENCOUNTER,RTL-COMPILER),

TANNER.

WORKSHOPS ATTENDED

. MEMS TECHNOLOGY AND APPLICATIONS - "MEMSTA-09" at Rajalakshmi

Engineering College, Chennai.

. "EMERGING RESEARCH TRENDS IN THIN FILM AND NANOTECHNOLOGY" at

Government College of Engineering, Coimbatore.

. VLSI EDA TOOLS UNDER "RACEE"-11 at Veltech Multitech Engineering

College, Chennai.

. Programmable System on Chip with "CYPRESS PSOC" at RMK Engineering

College, Chennai.

. VLSI Design using "CADENCE EDA Tools" at RMK Engineering College,

Chennai.

. "Hands on Training Design finishing for Chip Tape out" at RMK

Engineering College, Chennai.

. "System Verilog Workshop" at Exebit 2013, IIT-Madras.

. Integrated Electronic Circuit Education Using NI-Platform.

.

PAPER PUBLICATIONS & RESEARCH EXPERIENCE

. Efficient Prime Implicant Tabulation Method for Boolean Minimization

. Design of High speed array multiplier using BICMOS logic for driving

large load(IJCA)

. Design of GDI based 4-bit multiplier using Low power adder cells(IJCA)

. Nano Scaled Low Power Leakage ST-Based SRAM

(Published in IEEE Digital Explore)

. Involved in guiding the PG & UG level projects for the final year

students

. Analysis and design of BICMOS logic in 180nm Technology.

. Analysis of 8T SRAM using Dynamic cell supply

PROJECTS

1) S-RAM

Responsibilities: Design S-RAM, drawn the circuit in schematic, Layout

and

Verified DRC and LVS.

Platform : Cadence Virtuoso Schematic Editor, Layout Editor,

Assura

for DRC and LVS.

Technology : 180nm

2) 4-BIT MULTIPLIER

Responsibilities: Design Multiplier, drawn the circuit in schematic,

Layout

Editor Verified DRC and LVS.

Platform : Cadence Virtuoso Schematic Editor, Layout Editor,

Assura

for DRC and LVS.

Technology : 180nm

3) Efficient Prime Implicant method for Boolean Minimization

Responsibilities: Functional Simulation, Synthesis and Physical Design.

Platform : Incisive Simulator, Encounter RTL-Complier for

Synthesis,

and Encounter Digital Implementation for

Physical Design

Technology : TSMC 180nm

Personal Details

Father's Name : V.R.Nagendran.

Languages : Tamil, Telugu, English.

Date of birth : 12-08-1982.

Marital status : Married

Declaration

I hereby declare that all the information mentioned above is true to

the best of my

Knowledge.

PLACE: Chennai

(N. Arun Kumar)

DATE :

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