System Data

MUNAGA PADMA PRIYANKA

CORESPONDANCE Address:

#** & 18,

Sri Durga PG House for Ladies,

Vivekananda Layout,

Munnekolal,

Marthahalli

Bangalore - 560037

India.

Mobile : +91-886*******

Email : *****.*****.**@*****.***

CAREER OBJECTIVES

To grow as a learner and an efficient professional by enhancing my

knowledge and skills that leads to growth of the company and self.

EDUCATIONAL QUALIFICATION

. B. Tech (in Electronics and Communication Engineering) with aggregate

78.30% in 2010-2014 from ANNAMACHARYA INSTITUTE OF TECHNOLOGY AND

SCIENCES (JNTU ANANTAPUR),RAJAMPET.

. 12th with aggregate 90.2% in 2010 from Narayana Junior College (BOARD

OF INTERMEDIATE), KADAPA.

. 10th with aggregate 86.3% in 2008 from SAIKRISHNA E.M HIGH SCHOOL

(Board of S.S.C), KADAPA.

TECHNICAL SKILLS

Programming Language : C, VERILOG HDL,basics of java,

basics of html

Office tools : MS-office,

xlinx10.1 version,xlinx14.1 version, dev c++

ACADAMIC ACHIEVEMENTS

. Participated in paper presentation on EMBEDDED SYSTEM-THEFT MONITORING

CONTROL in madanapally institute of technical sciences, Madanapally.

. Worked as a class representative

. I have been played a lead role in college fest by conducting seminar

contests

STRENGTHS

1. Determined to learn with practical approach.

1. Good communication skills.

1. Enthusiastic in learning new things and can produce results under

deadline constraints.

1. Possess leadership quality.

1. Good at people management.

1. Positive Thinking.

2. Good verbal and written skills.

3. Good at problem solving.

4. Logical thinking

EXTRA CURRICULAR ACTIVITIES

1. Won 1st prize in caroms conducted in school.

2. Won 1st prize in school singing competition.

3. Organized various cultural programs in a club

4. Won prizes in quiz competition

ACHEIVEMENTS:

1. Got 28490 rank in GATE 2014.

ACADEMIC PROJECTS:

Topic : Simulation and Synthesis of 32-bit Unsigned Multiplier

Duration : 2 months

Team size : 6 members

Role : Team Leader

Description : It helps to provide fastest multiplication between two

unsigned 32-bit numbers using add and shift algorithm. In this adders

we are using are CARRY SELECT ADDER (CSLA) and CARRY LOOK AHEAD ADDER

(CLAA) .by performing multiplication using this two adders and compare

the delay, area and result for best adder for fastest multiplication.

SOFTWARE : XLINX10.1

VERSION

SIMULATOR : ISE SIMULATOR

PROGRAMMING LANGUAGE : VERILOG HDL

OTHER PROJECTS:

TOPIC : LOW COST SCAN CHAIN BASED TMR FOR MULTIPLE ERROR RECOVERY

SYSTEM

DURATION : 1 month

TEAM SIZE : 1 member

Description : it helps to provide multiple error recovery in a

TMR(Triple Modular Redudancy) . In an system any errors occur in the

modules may cause damage to the system which will be risk factor in safety

critical applications. By using this SMERTMR(SCAN CHAIN BASED TMR FOR

MULTIPLE ERROR RECOVERY SYSTEM) we can recover multiple errors present in

the system which is the advantage in health monitoring system and some

mines. SMERTMR is the advanced system of SCTMR where SCTMR can recover only

one error in the module but in case of SMERTMR it can recover more than one

error which will be very useful in advanced systems and also these TMRs

detect permanent errors in the system.

SOFTWARE : XLINX10.1 VERSION

SIMULATOR : ISE SIMULATOR

PROGRAMMING LANGUAGE : VERILOG HDL

PROJECT ON C:

TOPIC : BIT ERROR CORRECTION USING VITERBI DECODING AFTER

ENCODING THE DATA.

DURATION : 1 month

TEAM SIZE : 1 member

Description : it helps in decoding the encoding bits .In decoding the

errors occurs in the channel will be decoded and corrected using Viterbi

decoder .Here encoding of the data is done by using TRELLIS diagram and the

encoded data is passed through channel during transmitting in channel there

may cause some disturbances which will corrupt the data.in order to

retrieve data it is passed through Viterbi decoder which will correct the

corrupted data and gives as a output which will be very useful in

communication system. By comparing output of decoder with given data we can

analyze bit error rate.

SOFTWARE : DEV C++, XLINX10.1

VERSION

SIMULATOR : XLINX PLATFORM STUDIO

PROGRAMMING LANGUAGE : C

PERSONNAL DETAILS

Name : Munaga Padma Priyanka

Father's Name : M.Rangaiah

Date of Birth : 19-03-1993

City of birth : Kadapa

Sex : Female

Marital Status : Single

Languages known : English, Telugu, Hindi

Hobbies : Listen to Music, Reading books, Gardening,

drawing

Place : Kadapa

(M.Padma Priyanka)

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