PRADEEP G CHAGASHETTI

Email id:-acpaqf@r.postjobfree.com

Contact Number:-+91-974*******

Career Objective

To be associated with a progressive organization that provides an opportunity to apply my knowledge and skills in

order to keep abreast with latest trends and technologies.

Core Competency

Good understanding of fundamentals of Transistors.

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Good knowledge of Verilog RTL coding.

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Good knowledge of Digital Design Concepts.

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Good knowledge of Analog Design.

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Education

Examination University/School Year Class Obtained Percentage M.Tech in VLSI R.V. College of First class 70%

Design and Engineering, VTU. 2012-2014

Embedded Systems

B.E in E &C R. L. Jalappa Institution 2007-2011 First class 62.99%

of Technology

Karnataka State K. L. E PU college 2005-2007 First class 70.50%

Pre university Bangalore-560010

board(PUC)

Karnataka state K.V.V High 2004-2005 First class 76.16%

Secondary school Bangalore-

Education Board 560040.

(10th )

Paper Published

Pradeep G. Chagashetti, Dr. H. V. Ravish Aradhya, “Design and Verification of Analog Phase Locked

Loop Circuit,” Published in International Journal of Combined Research and Development”, volume 2, issue 6,

June 2014, pp 1-5.

Academic Projects

Title “GSM MODEM BASED BOMB DETECTOR USING EMBEDDED SYSTEM ”

Organization R.L. Jalappa Institute of Technology

Duration in 6

Months

Description The main aim of the project is to save the innocent people from getting hurt and to

help the world by using new technologies. The core of the project is to sense the bomb

from 10 meters and send sms to the bomb squad team for the defusing of bomb through the

GSM Technology and it will announce the presence of bomb in the present area.

Tools Used Micro Controller 8085, GSM modem, Sensor.

Title “AN ARITHMETIC LOGIC UNIT DESIGN BASED ON REVERSIBLE LOGIC

GATES”

Organization RV College of Engineering.

Duration in 3

Months

Description In conventional computers are irreversible. That is, some information about the

inputs is erased every time a logic operation is performed. The loss of information is

associated with laws of physics requiring that one bit of information lost dissipates kTln 2

of energy. A function is reversible if each input vector produces a unique output vector.

An important property of reversible circuits is that they can reduce the energy

consumption but reversible circuits consume very less power. In this project designing a

reversible ALU by using reversible gates to reduce the power usage of a present ALU then

it as applications in building reversible ALU, reversible processor.

Tools Used Cadence RTL Compiler and model sim 10.1.

Title “IMPLEMENTATION OF ARITHMETIC OPERATIONS AND SERIAL

COMMUNICATION THROUGH MSP430”

Organization RV College of Engineering.

Duration in 4

Months

Description The main aim of the project is serial communication through MSP430 and to

arithmetic operations which is mainly used for data transmitting and receiving to reduce

the processer area.

Tools Used IAR Embedded Workbench Version 5.5.

Title “DESIGN AND VERIFICATION OF ANALOG PHASE LOCKED LOOP CIRCUIT”

Organization RV College of Engineering.

Duration in 10

Months

The main of the project is to simulate the result of PLL circuit in CADENC (gpk180nm)

Description

tool and provides the result by phase locking of signal at the range of 140MHz. The lock range is

optimized to 2.19µs. The capture range of PLL circuit is 50MHz to 130MHz.The average power

consumed in the PLL circuit is optimized to 2.99mW.

Tools Used Cadence 180nm.

Personal Profile

Name Pradeep G. Chagashetti

Date Of Birth 05/March/1990

Father Name G. G. Chagashetti

s/o G. G. Chagashetti,No.32 sangameshwara nilaya,2nd main, B C C

Address

Layout,Vijayanagar,Bangalore-40

Nationality Indian

Sex Male

Languages English, Kannada and Hindi.

known

Software/Computer Proficiency

Language Programming in C.

Operating System: Windows Family.

Application Office 2007.

I hereby confirm that the above information is accurate to the best of my knowledge and belief.

PRADEEP G. CHAGASHETTI

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