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Engineer Design, test, Blutooth Low Energy, LabView,,test scripting

Location:
Jefferson City, Missouri, United States
Posted:
April 20, 2015

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Resume:

NISHANTH ANANTHA

acpage@r.postjobfree.com ***1 W Gardenia Drive, Peoria IL 61615 213-***-****

EDUCATION

University of Southern California, Los Angeles, CA May 2014

Master of Science in Electrical & Electronics engineering- VLSI & Computer Architecture GPA(Major) 3.53/4.0

GPA(Overall) 3.32/4.0

Courses Taken: Digital System Design: Tools and Techniques, Diagnosis and Design of Reliable Digital Systems,

VLSI System Design (Part A and B), Real Time Operating Systems, Semiconductor Physics

SKILLS

Software Languages: Verilog, System Verilog and Object Oriented Programming, VHDL, BSDL, Perl,Tcl, Python, C, C++,

Object

ect Python,

hon,

LabView CVI, MATLAB

Assembly Languages: Intel: 8085, x86, 8051; Analog Devices: BF535; Texas Instruments: TMS320C54xx, Motorola MP535

Tools:

Tools: ScanExpress, Altium Designer, OrCAD, Xilinx-ISE, Vector CAN Suite,ClearQuest,ClearCase, Cadence, Hspice,

Xilinx-ISE, Caden

Modelsim, GIT

Design

Design Standards: PCIe, I2C, DFT, DFM, J-TAG and Boundary Scan, IEEE 802.11, SPI OSI Model

Boundary

undary

CERTIFICATION;

CORELIS

CORELIS certified Boundary-Scan and ScanExpress tool suite professional

too Jul 2014

• Expertise in industry standards : IEEE 1149.x, DFT, JTAG, BIST and ATPG

Expertise DF

• Utilized ScanExpress TPG, Runner, ADO for system level(PCB) verification using scan chain insertion and test

pattern generation (TPG) scripts to test CPLDs, CPU, FPGA s, NAND and NOR flash memories

• Executed infrastructure testing, interconnect testing,cluster testing present in the scan chain using ScanExpress

Executed testing

WORK EXPERIENCE

Senior Engineer – Caterpillar Inc (Client), Peoria, IL Oct 2014- Present

• Embedded C test development and software unit testing on dSPACE ATEs

Embedded testing

ng

• Test environment development, including Python script development

Test script

• Improved the test scripts and driver files based on statistical analysis of test data

statistical

• Performed test setup analysis using schematics to improve software testing

• Complied with Agile and Six Sigma software design standards

Co-op: Hardware Development – St Jude Medical, Sylmar, CA Jan 2014- Jun 2014

• ATE test bench setup development for heart pacer IC and wafer testing

ATE

• C based automated test scripts development using LabView CVI

based LabView

• Developed LabView GUI to implement spectrum analyser functions to generate power spectrum response of RFICs

Developed analyser

• Performed PCB board soldering, verification and probe testing

Performed probe

• Executed Low Energy Bluetooth RF characterization tests for pacer ICs

Executed t

• Complied with FDA regulation standards in all documentation

Senior Engineer- Volvo Group Trucks Technology (GTT), Bangalore Jul 2009-Jul 2012

• Performed system, sub-system and unit level testing to simulate vehicle environment on LabView RT

• Built a highly complex compact-RIO based LabView real-time ATE (hardware in loop), along with the team

Built real-time

• Developed automated test scripts to verify truck functionalities using LabView(NI Test stand, Test suite)

Developed functionalities

nctionalities suite)

• Tested bluetooth audio and other infotainment systems in Volvo trucks

Tested systems

• Interacted with vendors for components’ procurement and BOM creation

and

• Contributed in global design reviews of truck functionalities like truck infotainment ECUs and telematics

Contributed funct

• Complied with ISO 9001:2012 test standards in all documentation

PROJECTS

ATPG module design in the FPGA Test System for Arbitrary Logic Functions (designed using CLBs) Nov 2013

• Constructed arbitrary schematic, using ISCAAS net list on FPGA

• Developed modified PODEM algorithm for test pattern generation using C and data structures

System identification using Blackfinn DSP processor (VisualDSP++/Embedded C) Sep 2008

• Implemented BF535 code to accept system and error co-efficients and to identify a system using LMS algorithm

• Developed digital FIR and IIR filter design using Analog Devices tool VisualDSP++, on EZKit setup

Dec 2013

UVM based 2 clock FIFO RTL design verification (QuestaSim, System Verilog/UVM)

Performed code coverage and constraints verification of design, test bench design

VHDL design of 32 bit out of order execution (Tomasulo) processor with speculative branch handling design Jul 2013

Implemented dynamically scheduled MIPS ISA instruction processor, executed out of order, retired them in-order

Designed units of Tomasulo processor such as Physical Register File, 2 stage Dispatch Unit, Free Register List,

CFC buffers(functioning as F-RAT), Re Order Buffer, Issue Q, Issue Unit

Integrated the design to simulate and synthesize using Modelsim and Xilinx respectively

J-TAG based RTL design for test (DFT) using Verilog Jan 2014

Implemented Design For Test (DFT) based RTL design,with scan cell insertions at boundary of RTL code blocks

DDR2 Memory Controller using 45nm VLSI technology (UNIX/NCVerilog) Nov 2013

• Implemented DDR2 memory controller RTL for 32 MB Micron SDRAM IP, used Synopsys Design Compiler

Executed Static Timing Analysis using PrimeTime, Auto Place & Route using SOC Encounter

FPGA Prototyping using ASIC and FPGA synthesis flows Nov 2013

• FPGA flow: Synthesized on Spartan6 FPGA, power estimation and timing path check using PlanAhead

(XILINX),optimized design to meet design constraints

• ASIC Flow: Synopsys-Design Compiler and PrimeTime to estimate area, power, and timing for synthesized design

Jun 2013

Chip multi-threaded (CMT) processor design on Spartan 6 FPGA

• Designed 6 stage pipelined in-order, fine-grain multi-threaded(4), CMT processor, synthesized on Spartan 6 FPGA

• Implemented CMT with thread selection, thread suspension, rollback, non-blocking cache using MSHRs

Jul 2013

Efficient 2 clock FIFO design using Block RAMs of FPGA

Efficient FIFO consumer side design using flow-through and pipelined BRAMs

Designed clock domain crossing depth calculations between the 2 clocks for producer and consumer sides

LEADERSHIP SKILLS

• Team lead role: Developed test plans, executed them, developed test reports; managed 2 consultants at Volvo

Team them, developed

• Contributed in global design reviews of truck functionalities like Bluetooth audio and telematics

ACHIEVEMENTS

• Awarded "Patent Idea of the year" at Volvo for the idea "Use of Blue Eye technology for driving environment

customisation in trucks”



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