Design Project

CHETAN

Email : ***********@*****.*** Ph: (M) +** – 895*******

OBJECTIVE

To achieve a challenging position in the SoC design and verification domain and to contribute to the

success of the organization through work and experience; taking up challenges and opportunities to learn

and enrich self technically and professionally.

EXPERIENCE SUMMARY

Internship Experience of 11+ months in Development of IP/Subsystem Frontend Package.

Worked as a Intern in STMicroelectronics, Greater Noida from January 2014 to December 2014

Experience on Frontend flow including SPYGLASS, Synthesis, timing closure for ASIC based

designs

Good understanding of Clock Domain Crossing, Power intent (UPF) concepts.

TECHNICAL SKILLS

Knowledge of ASIC Flow Design – RTL Design, Synthesis, Static Timing Analysis, Floor planning,

Placement and Routing

Languages known – verilog-HDL and C/C++

Tools Used – Design Compiler (Synopsys), PrimeTime (Synopsys), Atrenta SpyGlass, Cadence

Virtuoso

EDUCATIONAL QUALIFICATION

M.Sc. Tech in VLSI Design from SOIS, Manipal Academy of Higher Education in Dec-2014 with

CGPA 8.94/10

Advance Diploma in ASIC Designing from RV-VLSI Design Centre, Bangalore

B.E (Electronics and Communications) from GAT, VTU in 2011 with 72%

12th from GNPUC Bidar, Karnataka PU Board in 2007 with 85.67%

10th from Guru Nanak Public School Bidar, Karnataka, C.B.S.E in 2005 with 77.8%

EXPERIENCE

Organisation: STMicroelectronics Pvt Ltd. (Jan 2014 – Dec 2014)

Project Title: USB 3.0 Frontend Flow

Description: Development of Frontend Package for a HSI Subsystem

Responsibilities:

Design Intern in STMicroelectronics Greater Noida.

Complete responsibility of learning timing, synthesis and low power design concepts for

understanding of how to develop a fully functional package of a subsystem

Given the Responsibility to understand Standard Frontend Flow, and also the SpyGlass lint and clock

domain crossing concepts.

Have hands on in the SpyGlass lint and CDC checks on the design at the RTL/Netlist level.

Bug reporting and tracking.

Well trained by skilled designers.

ACADEMIC PROJECTS

1. Project Title: Segmentation Based Serial Parallel Multiplier

Technology: verilog HDL, Xilinx ISE Design Suite 13.1

Description:

The segmented based SPM architecture is efficient in throughput and speed. The new proposed

architecture minimizes the hardware resources. The proposed multiplier is based on a segmentation

technique of a simple SPM to blocks of equal bit length. This multiplier achieves higher throughput.

The segmentation based SPM uses two blocks MB 1 and MB2. It segments the computation i.e. the lower

bits and the upper bits of Product is computed in different segments or blocks

2. Project Title: Implementation of Musical CPU using FPGA Altera Board

Technology: verilog, Quartus, Xilinx, Altera Cyclone Board

Description:

A target Instruction set is designed to implement a circuit that generates square waves at specific frequencies

based on user input and play a tune on commonly available FPGA hardware. Eventually a CPU that uses

various instruction types to literally describe the sounds and flow of the music is achieved.

3. Project Title: Voice Mail system using internet protocol (VoIP)

Description:

VoIP (voice over IP - that is, voice delivered using the Internet Protocol) is a term used in IP telephony for a

set of facilities for managing the delivery of voice information using the Internet Protocol (IP). In general,

this means sending voice information in digital form in discrete packets rather than in the t raditional circuit-

committed protocols of the public switched telephone network (PSTN).

PERSONAL DETAILS

Date of Birth : 25 August 1989

Sex : Male

Nationality : Indian

Languages Known : English, Hindi, Kannada

: #302, MIG-B6, Suryanagar 1st phase,

Present Address

Anekkal Road, Chandapur, Bangalore,

Karnataka-560099

CHETAN

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