VLSI ENGINEER

A.KAYALVIZHI,

D/O T.D.Asokan,

**/**, ************* ******,

Thondamuthur,

Coimbatore-641 109.

Mobile: +91-950*******

Email Id:************@*****.***

Career Objective

To have a well challenging career and adopt with the growth of organization with my skills and obtaining a successful future in development.

Educational Qualification

COURSE

INSTITUTION/BOARD

PERCENTAGE YEAR OF PASSING

M.E(VLSI Design)

Adithya Institute of Technology

7.876(up to 3rd sem)

2015

B.E(Electronics and Communication Engineering)

Coimbatore Institute of Engineering and Technology

8.58(1st class with Distinction)

2013

HSLC

Government Girls Higher Secondary School

88.75

2009

SSLC

Government Girls Higher Secondary School

87

2007

Area of Interest : Digital electronics, VLSI, Electromagnetic Interference and

Compatibility

VLSI Software Skills : Modelsim, Quartus,Xilinx,Mentor Graphics,Tanner, Cadence

Microwind and Dsch

Other Software Skills : Multisim and Matlab

Programming Skills : C, VHDL and Verilog Programming

Hardware Skills : FPGA, Logic Analyzer and ARM Processor (Basic)

Operating System : Windows98/xp/7/8 and Ubuntu

Skills in Equipments : Knowledge in operating CRO and DSO

Academic Project:

B.E: Hardware Architecture for Intrusion Detection System

Description: Network security is a large and growing area of concern for every network. The main function of Intrusion Detection System is to protect the resources from threats. Various algorithms have been developed to identify different types of network intrusions.

M.E: Design of Multi-Bit Flip-Flop for digital circuits using Look-Ahead Clock-Gating

Description: Power has become a burning issue in modern VLSI design. Merging single bit flip-flops into one Multi-Bit Flip-Flop avoids duplicate inverters thereby lowering the total clock power consumption and the total area occupied. Look-Ahead Clock Gating (LACG) technique to further lower the total clock power consumption of merged flip-flops that share a common clock enabling signal.

Co-Curricular Activities

Paper and project Presented:

i)Smart Riding System, National level technical symposium 2012, SNSCE, Cbe.

ii)Wireless Sensor Network for Home Health Care, Intra department competition at CIET, Coimbatore on August 2012.

iii)Wireless Break Alarm, Intra department project competition 2012 at CIET.

iv)Hardware Architecture for Intrusion Detection System, National Conference on Emerging trends in VLSI, Signal Processing and Communication 2014 at UIT Cbe.

v)Design of Multi-Bit Flip-Flop (MBFF) for Digital Circuits, International Conference on Recent Trends in Electronics, Communication and Computation Technologies (ICRTECCT’15) March 2015 at SREC Tirupur.

vi)Design of Multi-Bit Flip-Flop (MBFF) for Digital Circuits using Look-Ahead Clock-Gating(LACG), National Conference on signal processing, communication and VLSI Design(NCSCV’15) April 2015 at Anna University Regional Centre, Cbe.

Workshop Attended:

i)Two days Hands-on training on FPGA implementation of digital systems using Altera Quartus II at Anna University, Coimbatore on Feb 2014.

ii)One day workshop on CMOS layout design flow using Microwind conducted by Virtual Technologies at MCET, Coimbatore on March 2014.

iii)Two days workshop on VLSI design flow using Microwind Tool at Anna University Coimbatore on August 2014.

iv)Two days National level workshop on IC design flow using Mentor Graphics tool in association with CoreEL Technologies at PSGCAS October 2014.

v)Three days Engineering Faculty workshop conducted by Wipro Mission10X at Adithya Institute of Technology on March 2015.

Other Co-Curricular Activities:

i)Participated in Industry Connect 2012 on placement Readiness, organized by SECE on July 2012 in association with NASSCOM and ICT Academy of Tamilnadu.

ii)Participated in Three days Leadership Development Programme at Breakthrough Bangalore on July 2012.

Case Studies Done:

i)Analysis of various level of interference using microwave setup with horn antenna.

ii)Analysis of various level of interference using microwave setup with horn antenna and TDM as external input.

iii)Analysis of 11 kW on-grid solar systems & 0.5 kW off-grid solar systems.

iv)Analysis of co-channel interference and adjacent channel interference in FM receiver.

v)Analysis of testing a components using Cathode Ray Oscilloscope.

Achievements:

i)Got a first prize in District level Quiz competition conducted by Tamilnadu Science Organization.

ii)Participated in State level Quiz program conducted by Tamilnadu Science Organization.

iii)Got second class in Typewriting English conducted by Government Technical Examinations in Commerce, Feb 2008.

Hobbies & Interest : Listening music, Reading books, cooking and playing.

PERSONAL INFORMATION

Name : A.Kayalvizhi

Father Name : T.D.Asokan

Date of Birth : 30-07-1992

Father Occupation : Lift Operator

Nationality : India

Languages Known : Tamil, English (To know speak and write)

Kannada (To know speak only)

I hereby declare that all the information furnished above is true to the best of my knowledge and belief.

Place :

Date : (A.KAYALVIZHI)

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