Post Job Free
Sign in

Fpga/Asic/Hardware, Design, Test, Verification,Verilog Hdl,Vhdl, C/C++

Location:
Chicago, IL
Posted:
June 14, 2015

Contact this candidate

Resume:

Qiang Li

Email:acp7w4@r.postjobfree.com

Tel: 312-***-****

Objective:

Seeking FPGA/ASIC Engineer in Design, Test, Verification and Validation, and contributing my knowledge, skills

and experience for company’s growth

Technical Skills:

Languages: C/C++, java, tcl/tk, Python, MIPS Assembly

Hardware Description Language: VHDL, Verilog HDL, SystemVerilog

Tools: Modelsim, VCS, Xilinx ISE, Altera Quartus, Synopsys Design Compiler and Power Compiler, Synopsys

SPICE, CosmosScope, Cadence Verilog-XL and SimVision, Cadence Encounter, Cadence Virtuoso, Synopsys

Formality, Mentor Graphics, Calibre DRC, Calibre LVS, Calibre PEX, Cadence IC 6.1, Matlab

Skilled in understanding: Communication system, Digital signal processing, Waveforms

OS: Linux, Unix, Windows

EDUCATION:

Illinois Institute of Technology

Master of Electrical Engineering

Wuhan University

Bachelor of Electronic Information Science and Technology

Projects: (October 2013 – May 2015)

Implementation of a processor complex including CPU, cache, bus and memory

Design and simulate a 32-bit MIPS processor complex including CPU, cache, bus and memory for R-type, loads,

store and I-type instructions, with placement/replacement, dirty bit status, write hit, write miss, read hit and read

miss strategies

Low power by Unified Power Format(UPF)

Build a 8-bit adder for simulation and synthesis using UPF with Clock Gating(CG), Power Gating(PG), multi-Vt

and multi-Vdd techniques, which save more than 50% power

Optimize power and timing of a CPU using UPF with CG, PG, multi-Vt and multi-Vdd techniques

Tools: Modelsim, Design Compiler and Power Compiler

DCT implementation based on Algorithmic Strength Reduction and binDCT Algorithm

Design and simulate Discrete Cosine Transform (DCT) by Factorization based on algorithmic strength reduction

and binDCT approximation, respectively, using Xilinx ISE

Circuit Level Simulation and Delay/Power Estimation of ISCAS-85 c432 benchmark circuit

Implement Power Gating techniques by Single Footer insertion, Stepwise Wake-up, Two Pass Power Switching

Control, respectively, to measure circuit delay, dynamic power, static power, subthreshold leakage current, rush

current, wake-up time of ISCAS-85 c432 benchmark circuit

Tools: HSPICE, Monte Carlo Simulation

RTL level Power Reduction of pipelined Mobile Multimedia Processor

Implement Enhanced Clock Gating(ECG), Local Explicit Clock Gating(LECG), Automatic Clock Gating(ACG)

techniques, respectively, to reduce power consumption for pipeline stage registers between DC and EX stage of

the microprocessor

Tools: Synopsys Design Compiler and Power Compiler, Synopsys Formality, Modelsim

Draw and simulate a Multiplier circuit

Draw and simulate 5*5 Array Multiplier schematics with Power Gating and multi-Vt techniques using Dual Rail

Domino logic and Split Path Data Driven Dynamic Logic (sp--D3L), respectively, which save about 60% and 10%

power

Tools: Cadence IC 6.1, Synopsys HSPICE, CosmosScope

Design and Synthesize of Carry Propagation Adders

Design and synthesize 8-bit and 32-bit adders with carry ripple, carry select, carry skip and KoggeStone,

respectively, using dual Vt techniques

Tools: Cadence Verilog-XL and SimVision, Synopsys Design Compiler, Cadence Encounter, Synopsys

Formality

Draw and simulate some gates

Draw and simulate the schematic and layout of AND gate

Tools: Cadence Virtuoso custom IC design platform, Synopsys Formality ESP, Mentor Graphics, Calibre Design

Rule Checking(DRC), Calibre Layout vs Schematic(LVS), Calibre PEX, Synopsys HSPICE, CosmosScope

Computer Simulation for Digital Logic

Build a digital logic simulator using the C++ that is able to simulate nontrivial digital systems including CPU

Simulation environment consist of C++ compiler and the Golden Simulator

Attained student visa and relocated to the U.S.

STATE GRID Corporation of China (July 2008 – February 2012 )

Design and maintain the pumped storage power plant

Installed, operated and maintained the equipment including ABB circuit breakers, CONVERTEAM static

frequency converter, NR ELECTRIC protection & control circuit breakers, TOSHIBA power transformer

Designed and tested protection circuits and control circuits of the equipment



Contact this candidate