Engineer Design
Resume:
Mark A Azadpour
********@*****.***
SUMMARY OF QUALIFICATIONS
Extensive experience in RTL design, verification and co-emulation.
Architecting, implementing and collecting coverage for various TB’s.
Defining Verification Plan and mapping to requirements and actual verification entities.
Defect tracking and resolution to completion and closure of issues in both pre and post silicon environment.
Software Development methodologies and UML design paradigm:
Various verification architectures and verification methodologies.
Various languages such as SV (UVM), Vera, C++, C, Perl, TKL.
Veloce, Palladium dual top verification design for emulation. DSP, embedded coding and assembler design.
Developing co-emulation TB, and gate level simulation.
Power management and register testing.
PROFESIONAL EXPERIENCE
2013- Present (Longmont, CO)
Western Digital
Sr. Design and Verification Technical Manager
Technical lead for verification activities for a distributed team of 24 engineers in multiple sites engaged in IP development and verification of SoC for the storage industry. Architecting UVM based test benches for various blocks and functional coverage closure for CRT test benches and UVM-A emulation based development.
2012- 2013 (Houston, TX)
Azadpour Enterprises
Principle Engineer/Director
Engaged in consulting verification activates for ASIC, and emulation platforms using UVM, and RVM libraries for DDR controller, medical DSP, communication switches, and telecommunication chips.
2007- 2012(Longmont, Colorado)
Seagate Technology
SR. STAFF
Key Responsibility:
Leading verification effort companywide using verification plan, architecting TB, collecting functional coverage. SV development and UVM development for SoC’s. Verifying SSD chips at the SoC level and working with firmware teams.
2006- 2007(Clearwater, Florida)
Honeywell
PRINCIPLE ENGINEER
Key Responsibility:
Architecting chip level functional verification models of chipsets using systemVerilog (AVM), on Questa platform.
Lead for project. Designing drivers, monitors, scoreboards using assertions and AVM and predictors. Verifying an aerial navigation SoC.
2006 (Cary, North Carolina)
Qualcomm Corporation
CONSULTANT ENGINEER
Key Responsibility:
Managing efforts involved in verification of ARM based wireless modem chips with large number of peripherals. Verifying an internally developed processor in conjunction with a video processor and USB front end.
2005- 2006 (Colorado Springs, Colorado)
StarKey Lab
SR. DESIGN ENGINEER
Key Responsibility:
Digital Verification Lead for Monarch project. Duties included designing and implementing verification models in SystemC and SV and closing functional coverage for a DSP chip.
1997- 2005(Colorado Springs, Colorado)
Vitesse Semiconductor Corp.
SR. MEMBER of TECH STAFF
Key Responsibility:
Designing and verifying embedded ASIC’s for storage and communication markets with focus on SAS and SATA markets.
Hardware/firmware LZ77 encryption algorithm for remote KVM architecture.
Designing an OIF SPI-4 Phase II protocol complaint packet generator at 10GBPS with XGMII interface and fully verified the functionality.
Developing behavioural models in Verilog and test-benches in a mixture of Verilog, Perl, and C++ for verification.
Developing a socket based queue server software package with load balancing using Perl, shell scripts and RPC.
Company representative to Infiniband standard committee.
Verifying blocks of a 32-by-32 switch for communication market.
1993- 1997(Austin, Texas)
Motorola Inc.
SENIOR ENGINEER
Key Responsibility:
Verifying embedded systems.
Designing a cycle accurate chip simulator with firmware debugger including a four stage pipeline in C++ with GUI front end.
Developing assemblers using LEX and YACC & a COFF linker with reloadable code.
Writing firmware for custom DSP chips.
Creating test vectors for testers.
Designing modular evaluation boards with pluggable daughter boards for DSP chip validation.
Writing BFM’s for several blocks of an embedded ASIC for verification.
Creating behavioural models in VHDL.
Developing ATPG pattern to help verifying sample modem chips.
STAFF ENGINEER
Key Responsibility:
Leading efforts to verify ASIC’s, as well as supporting tools, software, and firmware packages aimed at large ASIC’s for Telecom and Wireless industry.
Writing PERL & ORAPERL scripts and other CGI Perl scripts with Visual Basic front end and Oracle DB backend for a Web based process control system and reject product management.
Representing Motorola at the ATM forum.
Managing test and verification team for an OC48 ATM cell processor ASIC with forward error correcting capability and in charge of managing application support team.
Writing firmware to support evaluation boards for ADSL family of chips for verification purposes.
1992- 1993(Austin, Texas)
Fisher Control Systems
DESIGN ENGINEER
Key Responsibility:
Developing and verifying software/firmware packages for microcontrollers.
Designing vertical Sybase databases aimed at optimal performance.
Architecting client/server software packages.
Managing customer requirement gathering activities, beta site selection, and supervising installation and other Software Engineering activities.
Managing customer relationships through system acceptance.
1988- 1992(Columbus, Ohio)
Asea Brown Boveri (ABB)
Project Manager
Key Responsibility:
Developing control algorithm and real-time software packages with relational databases on distributed-control systems for chemical and industrial use.
Architecting various relational databases.
Designing control packages using PID closed loop control and Statistical Process Control (SPC) algorithms.
Providing technical sale support and system definition to meet customer needs.
Various project management responsibilities including resource and schedule and delivery management.
System engineering work including electrical sizing and placement of HVAC and power sub-system.
EDUCATION
MBA, Regis University. 2012
M.S. in ELECTRICAL ENGINEERING. Ohio State University. 1990.
B.S. in ELECTRICAL & COMPUTER ENGINEERING. Ohio State University. 1988.
REFERENCES
Available upon request
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