Design Engineering
Resume:
ANSARI *
ARAFAT M. A. ANSARI
***** ********* ******, *******, **–94536 Tel.: 334-***-**** E-mail: acp6f7@r.postjobfree.com
OBJECTIVE
M.S. Graduate looking for full-time opportunities from July 2015 in the Field of ASIC Design.
EDUCATION
Electrical Engineering (VLSI) – MS: Enrolled in fall 2013 (GPA = 3.51/4), San Jose State University, CA, USA
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Major Coursework: ASIC CMOS Design, Digital System Design & Synthesis, High Speed CMOS Circuits, Advanced Computer
Architectures and SOC Design & Verification
o Electronics & Telecommunication – BS: Conferred in December 2012, Mumbai University, Maharashtra, India
Major Coursework: Analog/Digital IC design & Application, Micro-controllers/processors, Mobile Communication.
TECHNICAL SKILLS
o Programming Languages: Verilog(HDL), System Verilog, Python, Shell scripting, C/C++
o Design Tools: Cadence Virtuoso, Cadence Encounter, Synopsys Design Compiler, Synopsys Design Vision AutoCAD,
Altera Quartus II, Model-Sim, Eagle, Kiel-vision, AutoCAD
o Design Skills: RTL Design, Computer Architecture Design, State Machine Design, Analog Circuit Design, Digital Library
Design(CMOS level 45nm), Verification, STA & DTA, Layout, DRC, LVS, Place & Route
o Lab Tools: Multipurpose meter, CRO, function generator, DC power generator
General Softwares: MATLAB, CorelDraw, Photoshop, MS – Office, Open Office
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o Operating Systems: Windows, DOS, Linux, Machintosh
WORK EXPERIENCE
Aug’ 14 – Dec’14: Assisting an advertisement firm in social marketing of their website www.roombagger.com
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May’ 08 – June’ 08: Trainee, S. S. Natu Plastics & Metals Pvt. Ltd., Mumbai, Maharashtra, India
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Designed PCB and performed soldering of various SMDs on it for the controllers of high power D.C. motors
Performed quality checking of the various constructed circuits and calibration of various tools & equipments used in the
workshop
GRADUATE PROJECTS
Design & Basic Verification of L2CAP Layer of Bluetooth v4.1, spring’15: Designed the L2CAP (protocol) layer of Bluetooth
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v4.1 at RTL level with complex state machines and several FIFOs and performed the basic verification of same. The design
controls the channel and packet based transactions of the Bluetooth communication.
Spread Spectrum Search Engine, fall’14: Performed digital design using Verilog (HDL) and synthesis using Synopsys tools of
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a correlator block for a spread spectrum communication system. The block consists of 32 correlators (32 -bit each) which compare
the incoming samples with a generated PRN sequence and give 32 peak correlation v alues.
Montgomery Modular Multiplier (sub-threshold), spring’14: A digital circuit which can perform modulus multiplication built
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at CMOS (45nm) level working in sub -threshold region (low voltage & low power utilization) designed using Cadence Virtuoso
Ring Bus, fall’14: A custom specification bus consisting of 3 sub -busses (8-bits) implemented using state machines in Verilog
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(HDL) and verified using System Verilog. The sub -busses use various packets for communication and the arbitration is done by
token that is passed around.
SOC Design & Verification, fall’14: Designed the timer0/1 block using Verilog (HDL) and wrote verification test bench for the
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PWM block of LPC2148 micro-controller.
NIOS-II Pipelined Architecture, summer’14: A 5-stage pipelined Altera NIOS-II 32-bit RTL architecture (with data hazard
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detection and stalling unit) designed using Verilog (HDL) and synthesized using Synopsys tools
Design for Test, fall’14: Implemented a SCAN logic to perform SCAN check of a design and checked it with scan chain input.
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Synchronous Serial in Parallel Out, fall’14: A digital block consisting of a 64-bit shift register & FIFO that takes serial input of
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data and provides a parallel output of 64-bits and uses 2 flag push-pull model designed in Verilog and synthesized using Synopsys
tools. Cadence Encounter was used to perform the PnR of the project.
MIPS32 Pipelined Architecture, summer’14: A 32-bit MIPS RTL architecture with 5-stages of pipeline (with data hazard
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detection and stalling unit) constructed using Verilog (HDL) and synthesized using Synopsys tools
RCA & CLA, fall’14: 8, 16 and 32 bit adders designed using different techniques on Verilog (HDL) at RTL level and
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synthesized using Synopsys tools and performed STA & DTA on the same
UNDERGRADUATE PROJECTS
o AIGR- Autonomous Intelligent Guided Robot, 2012: A project employing multiple sensors for detection of obstacles and
performing response actuations.
o Offline UPS, 2009: Uninterrupted power supply for providing 240 volts - 50 Hz supply in absence or failure of mains
ANSARI 2
CERTIFICATIONS
o Obtained A+ grade in Computer Hardware Technologist course at ReiNet Institute, India
o Obtained 70% marks in the Maharashtra State Certification of Information Technology exam, India
o Earned 2 professional days of Robotics at Robosapien workshop, India
o Attended a 5 days Personality Development workshop at Indo-American Society, India
AWARDS
o First Prize in Robo-War, Technical festival, Rizvi College of Engineering, India, 2012
o Second Prize in Robo-Soccer, Inter-college technical festival, Vivek Anand College of Engineering, India, 2012
o Second Prize in Robo-War, Technical festival, Rizvi College of Engineering, India, 2011
Second Prize in Fifa-Bots, Inter-college technical festival, Xavier’s College of Engineering, India, 2011
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EXTRA-CURRICULAR ACTIVITIES
o Served as the coordinator for technical festival, Rizvi College of Engineering, India, 2012
o Elected as class representative consecutively for 2 years, M. H. Saboo Siddik Polytechnic, India, 2007-2009
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