Engineer Design
Resume:
Bithika Das
Action Ct
*************@*****.***
Fremont, CA 94539
Seeking Position As:
Hardware Engineer
Hardworking, honest and result driven electrical engineer has proven technical expertise and
interest in this dynamic industry. Excels in hardware language, programming, scripting, troubleshooting,
digital system and schematic design, specification development and documentation, simulation, strategic
planning and implementation, modeling, integration and testing. Demonstrates optimistic attitude in
performing and completing projects despite high pressured environment and initiative to learn and adapt
with the software, applications and procedures employed in the organization. Recognized as a quick
learner and dedicated professional capable of working in minimal supervision and consistently maintains
work productivity. Exhibits passion and interest in engineering field and drive to constantly develop
knowledge on emerging trends.
Adept in Multi Tasking Proficient in VLSI, Digital Design Methodology
Outstanding Analytical Skills Proficient in Verilog, Simulation, Synthesis, STA
Flexible Team Player Mastery in schematic, Place &route, LVS, DRC
Exceptional Verbal & Written Skills Mastery in Parasitic Extraction and layout tools
Professional Experience
INTEL Corporation May 2014 –
present
Product Development Engineer
Santa Clara, CA
Responsible for serial I/O (PCIe Gen1/2/3) validation on server product.
Test Program developed in Python to validate PCIe Gen1/2/3 on Post Silicon.
Test time reduction and test flow improvement using Python for test cost reduction.
Debug, Test, Trouble Shoot & Convert Design Simulation vectors into product specific vectors
Producing product test plan, determining test spec by data analysis and representing test team
as well as setting up bench test for accurate device design Correlation.
Debug, Analyze, Collect data on post silicon test procedures.
Responsible for DeEmbedding, Calibration for SerDes RX test.
Responsible for PreSilicon validation for bug findings and methodology testing.
Worked on Power On for the latest server product.
INTEL Corporation July 2011 –
April2014
Graphics Hardware Engineer
Folsom, CA
Responsible for physical design of media partitions of 1.0 Million gates including all phases from
Synthesis to Final GDSII with 885 MHz with 14nm process technology.
Responsibility includes doing Physical Synthesis (Synthesis to Place & Route to Timing
Closure) using DC and ICC tools from Synopsys, placement, clock tree synthesis, routing,
timing closure, formal verification, physical verification and Signal integrity analysis.
Extensively analyze placement of cells, macros, units, metal routing in IC Compiler to improve
routing and timing during APR flows.
Implementation of ECOs for Bug, Timing Fixes, IR drop violations, Noise Violations and Caliber
violations
Intensively exercise Timing analysis using Prime Time Static Tool to close the timing for all
corners. Successfully close the target timing for each stepping.
Responsible for functional/Formal verification at unit level for RTL against post Place & Route
netlist as well as Gate to Gate FV using Conformal tool. Critical failing units are debugged,
procedures are written to resolve the functionally Failing units and the Abort units.
Experience in scripting language like TCL and Perl for the use of Design tools and debug flow
related issues.
NETLOGIC Microsystems:
June 2011 July2011
SerDes Analog Validation Intern
Santa Clara, CA
Involved in characterization of total jitter measurement (random jitter and deterministic jitter)
using J BERT
Involved in validation for SerDes Far End serial loop back using J BERT
MAXIM Integrated Products June 2007 –
Dec 2007
Strategic Applications Intern for Testing and Verification
Sunnyvale, CA
Involved in successfully testing new MAXIM products utilizing the MAXIM evaluation design kit
for cable TV network; familiarized on the use of various applications and software.
Verified RF immunity and provided detailed test reports based on the results after testing
various Maxim products; documented several tests made.
Developed and implemented testing methodology notes of Maxim product EV kit for the
customers; performed laboratory measurements for clients.
Education & Technical Skills
San Jose University, San Jose CA, 2011
MS in Electrical Engineering, GPA: 3.47/4.0
Curriculum Covered:
Advance Analog IC Design, RFIC Design II, ASIC CMOS Design & Synthesis, High Speed IC
Design, Semiconductor Devices, Principle of Semiconductor Device I/II, Probability and Statistics,
Broadband Communications Network, Linear Systems, VLSI Technologies.
San Jose University, San Jose CA, 2007
BS in Electrical Engineering GPA: 3.434/4.0
Curriculum Covered:
Analog CMOS IC Design, Field & Waves, Fundamentals of Networking, Operational Amplifier,
CMOS Digital Circuit, Electrical Design I/II, Theory of Automatic Control, Heat Transmission Theory,
Network Analysis, Digital Design I/II, Physics & Electronics, Principles of Electromagnetic Fields, Sr.
Design Project, Engineering Report.
Hardware & Software Experience:
Hardware Equipment Experience: J BERT, Network Analyzer, Spectrum Analyzer, Signal Generator
and Oscilloscope, Spectre Simulator.
HDL Language: Verilog HDL
Software:
Operating Systems: UNIX, Linux, Microsoft Office Suite.
Scripting Language: Perl, TCL TK, Python
Physical Design CAD tool: ICC, Design Compiler, Cadence Custom IC Design Virtuoso, Allegro
Timing Analysis tool: Prime Time Static Timing Analysis (STA)
Verification Tool: VCS, ModelSim, NCverilog, RTL Verification, Conformal
STATUS: US Citizen.
REFERENCES: References and proof of educational qualifications will be provided on request.
Contact this candidate