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Engineer Design

Location:
Bengaluru, KA, India
Salary:
According to company
Posted:
June 09, 2015

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Resume:

S.NIKILESH REDDY

CAREER OBJECTIVES

To obtain an active position in an innovative development environment as electronics engineer where I can use my skills for the potential growth of the organization and self with additional capabilities such as good interpersonal skills.

TECHNICAL SKILLS

Electronic Design Packages

Xilinx ISE,MODELSIM, CADENCE

Programming Languages

C, Verilog, System Verilog

Microcontrollers / FPGA

Spartan 6, Spartan 3E

Familiar Protocols

I2C,SPI

Familiar OS

Windows, Linux

EDUCATION

Name of

Degree

University/Board

Specialization

Year Pass Out

Aggregate

M.Tech

SRM UNIVERSITY, CHENNAI

VLSI Design

2014

79.29

B.Tech

N.B.K.R.I.S.T, Vidhyanagar, Nellore (dist), A.P

Electronics and Comm.

2012

71.2

12th

Intermediate State board,

A.P.

M.P.C

2008

87.2

10th

Board of Secondary education, A.P.

All

2006

80.5

Field Of Interest

Digital Design

FPGA

Digital Integrated Circuits

Analog Electronics

ACCOMPLISHMENTS

Participated in the PTS-ROBO-L1 Work shop (Building of autonomous Robots using Microcontrollers) conducted at N.B.K.R.I.S.T in association with PHOENIX TECHNOLOGIES & SERVICES.

Poster presentation on ZIG BEE (wireless network) in ECSTATICA at NBKRIST.

Participated in Social service programs (Member in EYE CROSS FOUNDATION).

PROJECT WORK IN M.TECH

MAJOR:

DESIGN OF CLOCK POLARITY STRUCTURE FOR CLOCK GATED DESIGNS:-

This Project Presents a Clock Polarity Assignment flow which permits post-silicon re-configurability.

A novel Clock Tree Synthesis (CTS) method is proposed that improves the reliability of an integrated circuit system through reducing the peak current on the power/ground rails dawn by the clock tree buffers.

The proposed CTS method entails the integration of XOR gates at one level of the clock tree to enable polarity assignment for peak current reduction.

The Power consumption in re-configurable (using XOR) is 50% less than when compared with polarity assignment (BUF/INV).

Tools used: CADENCE, XILINX

PERSONAL DETAILS

Father’s Name M.Subramanyam Reddy

D.O.B 24, September, 1990.

Current Address #2/18,room:no-10,opposite to Niranjan apartments, Thaverkere, Bangalore

Email ID ****************@*****.***

Passport Not Available

Contact No 089********

DECLARATION

I do here by declare that all the above statements are true to the best of my knowledge and belief.

Date: 09-06-2015

Place – Bangalore. Signature of the Candidate



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