High School Design

SANJAY JOSHI

E-mail:**************@*****.***

Mobile:+91-812*******

CAREER OBJECTIVE:

To excel in the chosen field of specialization and contribute positively to the organization.

EDUCATIONAL PROFILE:

Education

College

University

Duration

Percentage

B.TECH (ECE)

Sagar Institute Of Technology, Chevella.

JNTU, Hyderabad

2010-2014

70%

Intermediate (MPC)

Sri Chaitanya Junior Kalasala, Kukatpally.

Board Of Intermediate

2008-2010

76%

SSC

St. Xavier’s High School, Kukatpally.

SSC Board Of Education

2008

76%

SKILLS:

Programming Skills: C,core Java

Operating systems: Windows XP/Windows7,Redhat Linux

STRENGTHS:

Confident in approach, Self-Motivated.

Quick learner and Adaptable.

Goal focused.

ACADEMIC MINI PROJECT:

Title : IMPLEMENTATION OFBURST TRANSACTIONS USING OPEN CORE PROTOCOL.

Software : XILINX.

Description :

The Open Core Protocol™ (OCP) defines a high-performance, bus-independent interface between IP cores that reduces design time, design risk, and manufacturing costs for SOC designs. An IP core can be a simple peripheral core, a highperformance micropro¬cessor, or an on-chip communication subsystem such as a wrapped on-chip bus. The Open Core Protocol: Achieves the goal of IP design reuse. The OCP transforms IP cores making them independent of the architecture and design of the systems in which they are used to optimize die area by configuring into the OCP only those features needed by the communicating core and simplifies system verification and testing by providing a firm boundary around each IP core that can be observed, controlled, and validated.

The approach adopted by the Virtual Socket Interface Alliance’s (VSIA) Design Working Group on On-Chip Buses (DWGOCB) is to specify a bus wrapper to provide a bus-independent Transaction Protocol-level interface to IP cores. The OCP is equivalent to VSIA’s Virtual Component Interface (VCI). While the VCI addresses only data flow aspects of core communications, the OCP is a superset of VCI additionally supporting configurable sideband control signaling and test harness signals. The OCP is the only standard that defines protocols to unify all of the inter-core communication.

ACADEMIC PROJECT:

Title : SIMULATION OF AES ALGORITHM USING REVERSIBLE LOGIC GATES IN XILINX

Software : XILINX.

Description :

Advanced encryption standard (AES), a federal information processing standard (FIPS), is an approved cryptographic algorithm that can be used to protect electronic data. Here, we present a reversible logic implementation of a block cipher, namely, 128-bit AES. The various AES functional blocks have been synthesized using reversible gates, using which an overall reversible architecture has been proposed. The pipelined version as suggested can only be used in the Electronic code book (ECB) mode.The hardware complexity of the implementation has been evaluated using the number of reversible gates required and the quantum cost. This project is presented with regard to FPGA and the Very High Speed integrated circuit Hardware Description Language (VHDL).Xilinx 9.2i software is used for simulation and optimization of the synthesizable VHDL code. Synthesizable and implementation ( i.e. translate, map and place and route) of the code is carried out on Xilinx – project navigator. ISE 9.2i suite. The proposed architecture is suited for hardware- critical applications, such as ATM operations, secure networks, secure video, surveillance systems, defense applications, storage, devices and confidential corporate documents.

INTERESTS

Listening to music

Watching movies

Playing cricket

EXTRA CURRICULAR ACTIVITIES

Active participation in event organizing at school and college level.

Participated in two day national level work shop on “SIGNALS AND SIGNAL PROCESSING SIMULATION using MATLAB”,2k11.

Participated in two day national level work shop on “VLSI DESIGN & SIMULATION”,2k12.

ACHEIVEMENTS

Won the 1st Prize in MEMORY MONSTERS at BSTC TECHNOVISION, 2K13.

Won the 2st Prize in POSTER PRESENTATION at SAGAR TECH FEST, 2K13.

Won the 1st Prize in RUNNING RACE at ST.XAVIER’S HIGH SCHOOL.

PERSONAL INFORMATION

Name

Sanjay Joshi

Father’s Name

Suresh Joshi

Date of Birth

13-4-1993

Gender

Male

Permanent Address

S/O Suresh Joshi, L.I.G.H -725,

Road No.5,K.P.H.B Colony, Kukatpally,HYD-72

Declaration:

The above furnished information is true to best of my knowledge.

SANJAY JOSHI

Place: Hyderabad

Date:

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