Test Technician

Dwaine P. Laughlin

Phone: 505-***-****

Email: ******.********@*****.***

EDUCATION

BSEE - Colorado Technical University (GPA 3.2) 1990 to 1993

CERTIFICATIONS

IPC-A-610 Serial No. 38531495

Certification, Skolnik Technical Training Institute, October 2013

J-STD-001 Serial No. 18526159

Certification, Skolnik Technical Training Institute, October 2013

WORK HISTORY

Schweitzer Engineering Laboratories Inc. 2009 to 2011

Study of the Maxwell Equations: Elements of Engineering Electromagnetics,

sixth Edition 2006 to 2009

Maxim Integrated Products 1998 to 2006

Intel Corporation 1994 to 1998

OBJECTIVE

To demonstrate my abilities as a manufacturing technician in a company

where my experience and knowledge can be joined with others to produce a

competitive product.

QUALIFICATIONS

. Multilayer Printed Circuit Board Design; ORCAD, PADS.

. Programming; C/C++, Assembly, Extensible Markup Language (XML).

. Operating Systems used; Windows XP, Windows 2000, UNIX, DOS.

INDUSTRIAL EXPERIENCE

Schweitzer Engineering Laboratories Inc.

Test Development:

Wrote cable and harness test algorithms using C and implemented on CableEye

Tester. When required, built nonconventional load board tester interfaces

so new cable and harness configurations could be electrically verified

using the CableEye Tester.

Programming in XML generated code that measured individual DC component

values such as, diode forward voltage, reverse current leakage at reverse

voltage limit, DC resistance, drain to source resistance of field effect

transistors, and bipolar junction transistor junction testing. AC testing

involved frequency sweeps of low and high pass active filters involving

gain and phase margin measurements to determine filter response at

transition from passband through cutoff. Also, frequency sweeps of on

board chokes for voltage regulator current transient protection was

analysed to verify correct component placement. Simultaneous with test

script development, test fixture build was routinely done to reduce the

effect of unanticipated draw backs and increase the possibility of on time

project completion. The test fixtures were constructed to maximize test

coverage by jumper selection which set test parameters such as, clocking

speed, voltage references, and communications protocol indicated by

subassembly revision specification. Also, multiple port access supported

analog and digital testing, JTAG test, hardware configuration, firmware

programming, and power not supplied by tester were often required on test

fixtures.

Product Troubleshooter: Final Test

Received test failures of high, medium, and low voltage

microprocessor/programmable relay units requiring troubleshooting

subassemblies to component level along with various other communication

equipment implementing remote sensor processing capability. Frequent

problems found were bent pins on cable socket connections, pinched ribbon

cabling, missing or wrong component, bad soldering, damaged or misaligned

component(s) and solder splatter. These production incidents affected unit

power up, human machine interface (HMI) such as front panel display and

user input programming logic. Also, input-output (I/O) functionality such

as channel selection, I/O voltage protection, serial/parallel

communication, potential and current transformer readback and transformer

forward transfer characteristics measured input to output. Computer aided

schematic and component identification database access was used in locating

the problem subassembly and eventually the problem part when combined with

specific tester, operator fail comment, and tester fail data.

Maxim Integrated Products

Associate Engineer

Working for High Speed Signal Processing group my assigned projects were

from initial approach to completion. These engineering projects involved

BOM list development, ordering and gathering of parts followed by project

fabrication.

Design, with respect to wafer level test involved probe card layout; probe

pin length and count, metallic composition, and required AC bypassing and

choke protection in support of on-die test and laser trim measurement

stability. Test fixture design utilized separate planes usually placed at

physically different PCB areas and levels to support analog and digital

circuit performance. Consideration of circuit traces were, thickness,

routing length, separation, analog and digital ground plane placement and

their common point. Primary and secondary component surfaces on the test

fixture used through hole, for axial lead components and EMI shielding.

Surface mount part placement required pad orientation to reduce trace

congestion, cross talk, and provide power supply decoupling at the

respective pads. Also, foot printing of part due to package selection was

carefully considered.

Test and trim code development was simultaneously started with the board

build for project expedience to comply with the final date of completion.

Coding used Object Oriented Programming using C++.

Prior to component trimming the trim code would heuristically find the

optimal trim energy by use of on wafer dedicated trim calibration

structures to establish trim cut width and depth through test trim

algorithms. Test and trim coding measured in circuit die parameters such

as resistance, capacitance, reference voltage or current, and oscillation

frequency, to determine if active or passive trimming was required, and the

type of trim, such as, single/double plunge or 'L' cut, would be performed

on associated structures. Upon test trim completion a binning symbol, trim

revision, and lot identification would be placed in a designated areas on

the respective die.

As a product sustainer, modification of package sort test parameters such

as number of tests or test limits along with adjustments relative to wafer

sort test and trimming algorithms were routinely performed in support of

senior engineers as ongoing product development and changing functionality

of product after initial product release were required to meet ongoing

customer commitments.

Intel Corporation

Sustaining Technician Fab 3: Photolithography

Performed preventative maintenance (PM's) on the equipment such as Coaters

and Developers and ensured back up spin motors and replacement spin and

vacuum control boards were repaired and available to quickly get equipment

back into production. When not performing a PM on equipment, repair of

motor spin and vacuum control boards was done. Board repairs required

using multimeters for checking transistor junction, diode, resistor,

inductor, capacitive values and to measure DC voltages across the board.

Oscilloscopes were used to monitor motor current acceleration and

deceleration curves to isolate problem circuits or to monitor control pulse

generation to actuate solenoid switching needed in the process of moving

the wafer to and from the spin table.

Wafer Sort Technician

PM's involved test head calibrations on Trillium and Schlumberger GX9000

and FX9000 Pentium testers. Troubleshooting and (PM's) on Electroglas

probers involved eeprom system checks and repair to component level, planum

cleaning and programmed boundry fine tuning for forcer movement and reset.

Prober troubleshooting also included, wafer forcer orifice replacement,

equipment leveling, vacuum and pressure board solenoid switch

functionality, and digital to analog resolution (DAR) board repair to

component level .

Tools used on the job involved equipment such as digital multimeters,

oscilloscopes, spectrum and logic analyzers as well as other devices such

as PMU's to calibrate test system measurement accuracy and precision. Local

area networks were used to aid in remote monitoring of product and data

acquisition to an from the test floor increasing overall productivity.

Antistatic practices are always adhered to.

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