Design Engineer

A.V.S.R.L BHARADWAJ

Email id: **************@*****.***

Mobile Number: +91-970*******

Career Objective:

To work as an ASIC Engineer in a team oriented environment using cutting-edge technology, where I could learn and contribute my quality ideas and skills for the growth of the organization.

Core Competency:

Good knowledge of Verilog RTL coding, Digital Design Concepts.

Good understanding of fundamentals of Transistors and circuit theory.

Implemented VLSI projects during my postgrad.

Excellent knowledge of IC Fabrication process.

Good working knowledge of Linux, and C programming.

Strong communication, collaboration & interpersonal skills with proficiency in grasping new technical concepts quickly and utilizing them in an effective manner.

Good understanding of Analog, Digital circuits, Network analysis and Communication.

Good knowledge of ASIC and FPGA design flow.

Hands on experience on Altera Fpga Cyclone Variants.

Good Knowledge on ASIC Frontend and Back end design flows and corresponding tools.

Education :

Degree

Discipline

Institute

University

Year of Passing

Aggregate

PG

VLSI

V.N.R

V.J.I.E.T

2015

78%

B.Tech

Electronics & Communication

S.S Institute

of

Technology

2013

78 %

12th

Intermediate Board

Narayana junior college

2009

73 %

10th

Secondary school education

Bhashyam public school

2007

80 %

Academic Projects:

Title:

Implementation of ON-CHIP network protocol AMBA-AHB.

Role:

Design and FPGA implementation.(MTech. Final Project)

Description:

To design Master which randomly generates Address and Data,

Based on Address the decoding unit select a particular slave and series of write and read transactions take place with corresponding slave, eventually corresponding intermediate signals are asserted and de-asserted. FPGA implementation is done.

Tools Used :

Modelsim (Functional simulation),Quartus II for Synthesis & FPGA implementation

Synopsys Design compiler (Logic Synthesis),

ICC(place & route).

Title:

Synthetic Channel.

Role:

Design(Intern)

Organization:

Cerium Systems Pvt Ltd.

Description:

To design and analyse RS232 protocol for TFT module and programming Instructions for NIOS processor.

Tools Used :

Altera Quartus and Model sim.

Title:

Design and Functional verification of SORTER circuit.

Role:

Design.

Organization:

VNR VJIET (M.Tech.)

Description:

To design RTL for Bubble Sorting algorithm of a 4 bit number Sequence in Structural and verifying Functionality and bugs.

Tools Used :

Model sim, Xilinx ISE, synopsis - vcs, design compiler.

Title:

JOHNSON COUNTER.

Role:

Design of Schematic And Layout (Backend).

Organization:

VNR VJIET.

Description:

To draw the Schematic and Layout for counter and performing DRC and LVS.

Tools Used :

Mentor Graphics Design Architect and IC For Layout,synopsis-Icc.

ADDED ASSETS:

Worked as Intern in Cerium Systems Pvt. Ltd from September 2014.

Qualified GATE-2013 with ALL INDIA RANK 8786.

Personal Profile:

Name

: A.V.S.R.L BHARADWAJ.

Date of Birth

: 11/august/1992.

Address

: PT.NO – A/95,Phase -II,Allwyn colony, Kukatpally, Hyderabad.

Father Name

: A.V.S.G. KRISHNA MURTHY.

Nationality

: INDIAN.

Declaration:

I here by declare that all the above information given above is best of my knowledge.

A.V.S.R.L. Bharadwaj.

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