Engineer Design

VLSI Trained Engineer

ADEPU MOUNIKA

TECHNICAL SKILLS

Electronic Design Packages

Xilinx ISE, ModelSim,QuestaSim

Programming Languages

Verilog,System Verilog, C

Microcontrollers / FPGA

Spartan 3E, Spartan 6

Familiar OS

Windows XP,Windows 7

PROJECT WORK

1 DESIGN AND IMPLEMENTATION OF 16-BIT RISC PROCESSOR

Description: The Aim of the project is to design a 16 bit RISC processor and Implement on FPGA. RISC is a Reduced Instruction Set Computer, it performs 15 operations. Each Instruction takes four machine cycles to perform its operation. Instruction format has 4-bit for op-code, 4-bit for operand1 & 8-bit for operand2. It has 16-bit ALU and 16*16 Data memory. The sub blocks are modeled in Verilog and integrated to obtain the RISC processor top level module. The design is synthesized and targeted for Spartan 3E FPGA. Test plan is generated in order to debug the processor functionality with corner test cases.

Software Tools: Xilinx ISE, ModelSim Simulator

Hardware: Spartan-3E

2. DESIGN AND IMPLEMENTATION OF WHEEL CHAIR BY USING WIRELESS TECHNOLOGY

Description: The Aim of the project is to design and implement wheel chair for physically handicapped People. This design is based on Zigbee Wireless Communication Technology; it has transmitter block and receiver block. From transmitter block commands can be sending to receiver block through Zigbee. According to the commands microcontroller control the wheel chair movements.

Software Tools: Keil software, Flash magic

PROFESSIONAL COURSES

Completed Professional Development program, in VLSI design and Verification, from Sandeepani School of VLSI Design.

EDUCATION

Name of course

/degree

University/Board

Specialization

Year Pass Out

Aggregate

M.Tech (in class)

Jawaharlal Nehru Technological University – Hyderabad

Embedded System

2015

85

B.Tech

Jawaharlal Nehru Technological University – Hyderabad

Electronics and Communication

2013

74.6

12th

Board of Intermediate Education

MPC

2009

91.9

10th

Board of Secondary Education

SSC

2007

88.8

ACCOMPLISHMENTS

Got 2nd prize in Technical quiz in Balaji Institute of Technology & Science

.

PERSONAL DETAILS

Father’s Name : ADEPU PAPAIAH

D.O.B : 08/08/1992

Current Address : Kantha Residency, 92/2,27th main, BTM 1st

stage,Bangalore-68

Email ID : *******.*****@*****.***

Contact No : 903-***-****

DECLARATION

I do here by declare that all the above statements are true to the best of my knowledge and belief.

Place-Bangalore Signature of the Candidate Date-

Contact this candidate