M.Tech(VLSI Design)-VerilogHDL,VHDL,C language.
Resume:
OBJECTIVE
Seeking a challenging position in VLSI design and verification where my skills will greatly enhance the company's success and my personal growth.
ACADEMIC QUALIFICATION
COURSE
INSTITUTION
YEAR OF PASSING
CGPA/PERCENTAGE
M.Tech
(VLSI Design)
SRM University, Chennai.
May 2015
7.65
B.Tech (ECE)
Sri Manakula Vinayagar Engineering College, Pondicherry.
May 2013
7.53
Higher Secondary
St. Patrick MHS School, Pondicherry.
March 2009
76.58%
Matriculation
St. Patrick MHS School, Pondicherry.
March 2007
78.09%
AREA OF INTEREST
Digital Circuits
Verilog HDL
TECHNICAL SKILLS
Basics of C
VHDL
Verilog HDL
SOFTWARE TOOLS
Simulation Tool : ModelSim 6.3
Synthesis Tool : Xilinx ISE 14.3
Documentation Tool : MS Office(Word, PowerPoint)
PROJECT PROFILE
M.Tech
Title : Parallel-Pipelined Bit Reversal Circuit for MDC Architecture
Description : An efficient FFT architecture in terms of both area and performance with normal order . output is designed.
B.Tech
Title : High Speed Hybrid Carry Select Adder
Description : To design area efficient, low power consumption and high speed carry select adder.
ACHIEVEMENTS
Published “Bit Reversal Circuit for MDC Architecture” project in the Scopus indexed international journal IJEAR.
Secured 45th rank in Round 1 - Code Vita (2012) contest conducted by TCS.
Awarded Runner-up in project expo held at “SRM University”, Chennai.
CO-CURRICULAR ACTIVITES
Presented paper on “Airborne Internet” held at “C.Abdul Hakeem College of Engineering and Technology”, Vellore.
Attended workshop on “MIMO communication and networks” held at “SRM University”, Chennai.
Participated in project expo held at “Anna University”, Chennai and “Manakula Vinayagar Institute of Technology”, Pondicherry.
PERSONAL TRAITS
Good Leadership Quality
Interpersonal Skills
EXTRA CURRICULAR ACTIVITES
Infosys Campus Connect Training Program.
Business English Certification Training Program.
Active Member in N.S.S and Participated in the ten days Special Camping Programme.
Attended the Lecture series organized by IEEE Communications Society Madras.
PERSONAL DETAILS
Date of Birth : 01.02.1992
Father’s name : Mr. Rajkumar.P
Mother’s name : Mrs. Vimala Rajkumar
Hobbies : Cooking, Listening Music
Languages Known : English, Tamil, and Kannada
DECLARATION
I hereby declare that all the details furnished above are true to the best of my knowledge.
Place:
Date: (R.PRABAVATHY)
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