Engineering Systems

UMASHANKAR S. IYER

**** ***** ***** ****

Plano TX 75093

214-***-****(Cell) 972-***-**** (Home)

Email: *****.******@*****.***

Goal: To seek a challenging systems engineering role that uses my skills in System

Architecture, Signal Processing, Communications Wireless Systems and Embedded

Software Development.

Summary:

• Key entrepreneurial experience at startup company leading product definition, systems

development and customer interaction.

• Vital product development experience leading systems development for three major

products to successful RTP from specification to product ramp.

• Strong systems engineer with background in both wireless and wireline communications.

This includes RF Systems, Baseband Algorithm development, Digital Signal Processing

and Embedded Firmware development (TI C6x and 8051).

• Able to bring multiple disciplines together to successfully create a product. Includes

systems engineering/product definition, software development, digital design, analog

design and product test.

• Mobile app development to support M2M solutions

• Strong communications skills with excellent customer relationships.

EXPERIENCE

Indriya Networks LLC, Plano, Texas Jun. 2008 to present

• Founded of Indriya Networks specializing in GPS based asset tracking and monitoring

• Defined and developed system targeting infrastructure development companies to help

monitor operation of fleet of vehicles and equipment.

• System integrates GPS, GPRS modem, low power RF networks and sensors for

monitoring fuel, vehicle load and active RFID tags.

• Developed Android tablet based GPS tracking that integrates NFC tags for fleet

operations

• Developed embedded software for active RFID reader, tags and sensor boards based on

8051.

• Designed boards active RFID readers, tags and sensor boards.

Authentix Inc, Addison, Texas Apr. 2012 to Nov 2012

• System Consultant at Authentix assisting with development of image processing

algorithms for TI C64+ multicore DSP based platform

Umashankar Iyer *****.******@*****.*** 1/5

• Ported and modified algorithms from Matlab to be implement on the TI C64+. This

involved prototyping in fixed point and optimizing for real time implementation.

• Identified candidates for implementation and in C64 assembly (ASM) and worked with

ASM developer by providing test vectors

• Developed ASM routines for implementing image processing filters. Fixed bugs in

existing routines.

• Worked with HR in screening and interviewing candidates for Algorithm and Software

Development team.

Texas Instruments Inc., Dallas, Texas. Aug. 1996 to Jan 2008

Wireless Terminal Hardware Design Group - TI

Systems Manager (RF Transceiver 3G Radio) Aug. 2007 to Jan 2008

• Successfully led the definition of the architecture of a 3G radio, including algorithms for calibration

and compensation. Defined a scalable architecture that included support for 3G extension such as

dual cell reception and a platform for 4G.

• Firm understanding of cellular standards: 2G (GSM, GMSK), 2.5G (EDGE, 8PSK), 3G (wCDMA)

and 4G (LTE, OFDM). Well versed in modem algorithms to help optimize transceiver design.

• Lead systems interface with customers to discuss product requirements and gauge competitiveness.

• Responsible for coordinating with analog and digital designers and software development team to

ensure that design meets or exceeds the product requirement from performance, power and size

perspectives.

Mobile Connectivity Solutions - TI

Systems Manager (mDTV) Jan. 2005 to Jul. 2007

• Successfully lead systems development of the world’s first single chip mobile DTV receiver to a 1st

pass release to production.

• Responsible for defining product requirements, coordinating with the algorithm development team,

silicon designers and software development team to ensure that design meets or exceeds the product

requirement from performance, power and size perspectives.

• Lead interface with customers to discuss product requirements, present post silicon performance

updates, finalize interface issues and solve productization issues with module manufacturer.

• Responsible for lab bring-up/debug of OFDM baseband on the pre-silicon FPGA platform.

• Responsible for post silicon lab characterization and performance debug and optimization. Led

definition of production tests and yield improvement with the product engineering team.

Broadband Communications Group - TI Aug. 1998 to Dec 2004

Firmware team lead (UR8) Sep. 2004 to Dec 2004

• Software lead of architecture specification for next generation Client Premise Equipment (CPE)

modem. This involves specification of memory and MHz requirements, caching requirements for the

DSP, hardware software partitioning.

• Responsible for project schedule for modem firmware which includes both pre silicon and post

silicon milestones.

Firmware team lead (AR7) Sep. 2003 to Aug. 2004

Umashankar Iyer *****.******@*****.*** 2/5

Responsible for feature rollout roadmap, project schedules and development of DSP firmware for

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current generation TI DSL CPE products.

• Architected CPE Software Architecture to support multiple generations of DSL standards. This

included introduction of dynamic data memory management, aggressive code overlay techniques

and MIPS optimization.

• Responsible for guiding the team on improving the performance and stability of the modem. This

involved improvements to the equalization algorithm and timing recovery mechanism for the double

bandwidth ADSL2+ standard.

• Lead the team on interoperability of the next generation ADSL standard (ADSL2/2+).

• Coordinated development with a multisite team in Dallas, Texas and Bangalore, India.

DSL CPE Systems Engineer Aug. 1998 to Aug. 2003

• DSL CPE Physical layer tuning. Development and optimization of algorithms for timing recovery,

channel equalization, echo-cancellation and bit allocation. Porting code from Matlab/C floating point

models to C62 fixed point arithmetic.

• Extensive experience in programming on TI C6x DSPs. Development for blocks such as scramblers,

equalizers, constellation encoders and bit loading. Blocks performance optimized in both C and

assembly using TI Code Composer Studio.

• Intimate knowledge of DMT technology and DSL Standards.

• Interoperability of TI CPE DSL modems with TI and non-TI Central office modems.

• TI representative at ITU standards on DSL

PC Systems Laboratory - TI Aug. 1996 to Aug. 1998

Software Systems Architect Aug. 1996 to Aug. 1998

• Scalable video compression for POTS based video-conferencing.

• Multi-resolution texture maps for 3D computer graphics.

Michigan State University, East Lansing, Michigan. Sep. 1990 to Aug. 1996

Research Assistant, Adaptive Filtering Laboratory Sep. 1990 to Aug. 1996

• Developed algorithms for identifying very long impulse responses, typically for echo cancellation.

• Researching on a general structure for parallel algorithms for echo cancellation using multirate

techniques.

• Projects in speech processing involving estimation of LP parameters and pitch detection.

• Coding of algorithms for error detection and correction, transforms, and adaptive algorithms.

Teaching Assistant, Department of Electrical Engineering Sep. 1990 to Aug. 1996

• Teaching courses in electrical instrumentation, deterministic and probabilistic communications

systems.

• Developed and taught an electronics and communications lab for telecommunication majors.

• Assisted seniors in developing systems for coding and spread spectrum communications.

COMPUTER SKILLS

Unix, DOS

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Umashankar Iyer *****.******@*****.*** 3/5

C, C++, Java, Matlab, ClearCase, TI Code Composer Studio, Keil uVision, Eclipse, Android and

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IOS App Development and Code::Blocks IDE.

EDUCATION

Ph.D. Electrical Engineering, Michigan State University (MSU). Aug. 1996

Thesis: Polyphase-based Alias-Free Structure for Adaptive Filtering and Tracking

M.A. Applied Mathematics, Michigan State University. Aug. 1996

Emphasis: Coding theory, Numerical Analysis, Functional Analysis and Linear Algebra.

M.S. Electrical Engineering, Michigan State University. Mar. 1992

Emphasis: Signal Processing, Speech Processing, Communications Systems, Control Systems,

Estimation and Detection, Adaptive FIR and IIR filtering, System Identification, and Neural Networks.

B.Tech. Electronics and Communications Engineering, J.N.T. University, India. Jun. 1990

Emphasis: Communications systems, Signal Processing, Control Systems, and Computer Engineering.

Umashankar Iyer *****.******@*****.*** 4/5

PATENTS

Method of re-synchronizing data transfer between two modems connected by a dedicated line

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(Patent No. 6,707,902).

METHODS AND APPARATUS FOR CRYSTAL OSCILLATOR DRIFT ESTIMATION AND

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COMPENSATION (Patent App: 200********).

Receiver-side selection of DSL communications mode (Patent App: 200********).

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Upstream signal optimizer with a transmitter employing the same and a method of optimizing an

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upstream signal (Patent App: 200********).

PUBLICATIONS

Majid Nayeri and Umashankar Iyer, ``How good is the Adaptive Polyphase Structure,'' in

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Proceedings Of 34th Annual Allerton Conference, pp 526-535, Monticello, IL, Oct 2-4th 1996.

Majid Nayeri and Umashankar Iyer, ``Enhancements to the Adaptive Polyphase structure,'' in

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Journal of Circuits and Systems, Vol. 7, No. 3, Aug. -Sep. 1997.

Umashankar Iyer, Majid Nayeri, and Hiroshi Ochi, ``A Polyphase FIR Adaptive Structure for

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Adaptive Filtering and Tracking,'' in IEEE Transactions on Circuits and Systems - II Analog and

Digital Signal Processing, Vol. 43, No. 3, pp 220-233, Mar., 1996.

Hiroshi Ochi, Umashankar Iyer, and Majid Nayeri, "A Design Method Of Orthonormal Wavelet

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Bases Based On IIR Filters," in IEICE Trans. Fundamentals, Vol. J77-A, No. 8, pp. 1096-1099,

Aug. 1994.

Umashankar Iyer, Majid Nayeri, and Hiroshi Ochi, ``Parameter Tracking of the Poly-Phase Structure

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Adaptive Filtering Algorithm,'' in Proceedings of the International Symposium on Circuits and

Systems, Vol. 2, pp. 61-64, London, May, 1994.

Umashankar Iyer, Majid Nayeri, and Hiroshi Ochi, ``A Poly-Phase Structure for System

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Identification and Adaptive Filtering,'' in Proceedings of the International Conference on Acoustics,

Speech, and Signal Processing, Vol. 3, pp. 433-436, April 1994, Adelaide, Australia.

Umashankar Iyer, Hiroshi Ochi and Majid Nayeri, ``IIR Sub-band Adaptive Filtering,'' in

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Proceedings of the 36th Midwest Symposium on Circuits and Systems, Vol. 1, pp. 125-128, August

16-18, 1993, Detroit, Michigan.

Umashankar Iyer, Hiroshi Ochi and Majid Nayeri, ``Statistical Analysis of Multi-rate Filters with

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Stationary Inputs,'' in Technical Report of IECE, CS92-89 DSP 92-89, pp. 33-40, Jan. 1993, Japan.

HONORS AND AWARDS

Two National Merit Scholarships from the Government of India (1984 & 1986).

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Outstanding Graduate Student award from the College of Engineering, MSU (1992-93).

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Dean's Fellowship from College of Engineering, MSU (Summer 1993).

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IMMIGRATION STATUS

US Citizen

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Umashankar Iyer *****.******@*****.*** 5/5

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