Engineer Design

PRAPTEE PRADEEP JAMBHORKAR

**** ********* **, *** #*, Los Angeles, CA – 90007 267-***-**** ********@***.***

EDUCATION

MS in Electrical Engineering (GPA: 3.36/4) Aug 2013-May 2015

University Of Southern California, CA

B-Tech in Electrical Engineering (GPA: 3.98/4) Aug 2006-May 2010

Government college of Engineering, Maharashtra, India

RELATED COURSEWORK

MOS VLSI Circuit Design, VLSI Circuit Design, Computer system organization,

Design and Diagnosis of reliable digital system, VLSI System Design and Power Electronics

T ECHNICAL SKILLS

Programming Languages: C, C++, Verilog, Python, Perl

Workbenches: Cadence (Virtuoso), ModelSim, MATLAB

Application Software: Microsoft Office Suite, Pro-Engineer Wildfire, JMAG analysis tool

ACADEMIC PROJECTS

Developed Cardinal Bidirectional Ring NoC Router Mar-2015

Designed the Router using Verilog HDL and simulated using Cadence NCSim,

Synthesis was done using Synopsys tool (45nm Technology)

STA, Logic Equivalence verification and Placement and Routing

was done using PrimeTime, Conformal and SOC Encounter tools.

Implemented ATPG algorithms and verified the results with fault simulation techniques (using C) Nov-2014

Built a program to implement and verify ATPG algorithm for generating te st patterns

Obtained fault coverage of 98% for all the circuits tested (ranging from 80 to 1355 nodes)

Developed a 5 stage pipelined general purpose microprocessor in cadence, used Perl script to

generate test patterns and compare the analysis results with golden results Nov-2014

Custom designed a 5 stage pipelined CPU for performing arithmeti c and memory operations

Operating frequency of 0.3GHz was achieved, Perl script was used to implement control

Operations, test pattern generation and result verification

Modeled and tested 256 bit SRAM using Cadence Virtuoso: Nov-2014

Custom designed complete circuitry of 256 bit SRAM

Performed simulations to test the functionality covering all the corner cases

Design and analysis of 1 GHz Phase locked loop in Cadence: Apr-2014

Custom designed and simulated all components of a digital PLL

Performed simulations to obtain performance parameters

Lock time of 280.8nsec was achieved

Implementation of 5-stage Pipeline CPU using ModelSim: Feb-2014

Designed and verified a 5-stage in-order linear instruction pipeline with early

branch implementation based on MIPS ISA incorporating hazard detection, stalling,

forwarding and flushing mechanisms in Verilog.

WORK EXPERIENCE

University Of Southern California (Student Assistant) Sep 2013 -Present

Data handling, record management and report generation.

Larsen and Toubro (Senior Design Engineer) Aug 2010 -July 13

Project lead for multiple electrical and electronic projects including design and

testing of various frames of 3 pole and 4 pole contactors and its accessori es

Awarded as best performer for exceptional organizational skills and timely

delivery of complex projects

Patented 2 ideas in field of electromagnet actuation system and electromagnet based

mechanical latch system for low and medium voltage switching devices

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