Engineer Design

Qi Li

** ******** ******, **********, *** York, USA 13905

*****@**********.*** 607-***-****

EDUCATION

BINGHAMTON UNIVERSITY, THE STATE UNIVERSITY OF NEW YORK

Master of Science in Electrical and Computer Engineering, GPA: 3.65/4.00 Expected May 2015

Relevant courses: Computer Design, Computer Architecture, Digital System Design, Cmos VLSI Circuits &

Architectures, Digital Communication, System On A Chip Design, Hardware-Based Security

HEFEI UNIVERSITY OF TECHNOLOGY, HEFEI, CHINA

Bachelor of Engineering in Communication Engineering, GPA: 3.00/4.00 Graduated June 2011

Honors: Outstanding Student Leader 2008-2009

SKILLS

Computer: C++, C, Java, MATLAB, Verilog, Modelsim, Simulink, Microsoft Office, SQL

Foreign Languages: Mandarin Chinese (native), English

WORK EXPERIENCES

Beyondsoft Beijing, China

Testing Engineer August 2011-June 2013

Established the testing environment according to the testing procedure and plan.

Designed and carried out the test script and test case and observed scripts for any bugs.

Analyzed problems to properly position and certify solutions and submitted the bug report in standard format to

software developers, and then tracked and verified the bug to ensure the problems were solved.

Performed retesting and coordinated with colleagues to obtain a better understanding of the function

requirements of products to make sure standards were met.

EXPERIMENT PROJECTS

Final Project: Scalable Sentiment Classification for Big Data Analysis Using Naïve Bayes Classifier

Binghamton University September 2014- Present

Classified the Amazon movie review dataset into 5 subsets according to its 5-point rating system.

Utilized Java to implement the Naïve Bayes classifier (NBC) on top of Hadoop framework.

Evaluated the scalability of Naïve Bayes classifier (NBC) in large-scale datasets.

Dual Core Processor Design

Binghamton University February 2014

Designed dual core based processor architecture in Verilog and tested the power and latency.

Decomposed the project into small tasks and designed them to 3 other group members, and organized weekly

discussions to solve problems that arose.

Achieved parallel processing, and optimized missing penalty resulting in top 3 ranking out of class.

16-bit Adder Design

Binghamton University October 2014

Designed 16-bit carry look ahead adder, drew the layout in Cadence Virtuoso, implemented it with dynamic

Manchester carry chain, extracted the HSIPCE netlist and verified its function using CosMosScope.

Achieved best performance when add 1 to 1111111111111111, in which scenario the advantage of bypass gain

the most.

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