Engineer Design

PALLAVI SINGH

Contact: +91-956*******, 901-***-****; E-mail: *******.*******@*****.**

*******.********@*****.***

Profile: Design and Verification Engineer at Incise Infotech Pvt. Ltd from last 2.0 year.

SUMMARY

Good knowledge in digital design techniques

* Designing of AES

* Designing of LDPC general and with Min sum algorithm.

* Verification of AHB Protocol

* Good knowledge in:

* Specification development

* RTL Designing

* Micro Architecture Development

* Test plan Creation

* Software expertise

* Verilog

* System Verilog

* C

* Tools and Methodology

* Modelsim

* Effective team player with exceptional planning and execution skills coupled with a systematic approach and quick adaptability.

* Designation- Design and Verification Engineer.

Technical Skills

Programming Language

C

HDL Languages

Verilog, system verilog

EDA Tools

Modelsim

Operating System

Unix,Windows

EDUCATIONAL CREDENTIALS

M. Tech (VLSI Design), 2012

Banasthali University; 77.11%

M.Sc. (Electronics and Instrumentation), 2009

Dr. B.R. Ambedkar University Agra; 78%

Bachelor of Science, 2007

Dr. B.R. Ambedkar University Agra; 62.40%

Intermediate, 2004

Uttar Pradesh Board; 63.40%

Matriculation, 2002

Uttar Pradesh Board; 65.50%

Projects Undertaken

Title

LDPC

Organization

Incise infotech pvt. Ltd.

Tool

Modilsim

Details

Design a novel micro-architecture structures for check node message processing unit (CNU) for the min-sum decoding of Low-Density Parity-Check codes (LDPC). The construction of these CNU structures is based on a less known property of the min-sum processing step that it produces only two different output magnitude values irrespective of the number of incoming bit-to check messages. These new micro-architecture structures would employ the minimum number of comparators by exploiting the concept of survivors in the search. These would result in reduced number of comparisons and consequently reduced energy use.

Role

Designing of decoder using Min sum algorithm.

Title

AES (advanced Encryption Standard)

Organization

Incise infotech pvt. Ltd.

Tool

Modilsim

Details

AES is a data encryption/decryption standard required for the security of data transferred from transmitting end to the reception end. The project deals with the designing of the IP in Verilog, then the verification of the IP in System Verilog using UVM methodology. The project also involves the development of the virtual prototype of the IP in System C for software testing.

Role

Designing of Key Expansion.

Title

AHB

Organization

Incise Infotech pvt. Ltd

Tool

Modelsim

Details

AHB is a new generation of AMBA bus which is intended to address the requirements

of high-performance synthesizable designs. AMBA AHB is a new level of bus which

sits above the APB and implements the features required for high-performance, high

clock frequency systems including: burst transfers, split transactions, single cycle bus master handover, single clock edge operation, non-tristate implementation, wider data bus configurations (64/128 bits).

Role

Developed monitor for verification environment.

Summer Internship

Training on Electrical Generator at Jamuna Auto Delhi

Workshop Attended

Tanner Tools Pro-A Complete VLSI Design Software

Personal Profile

Father’s name : Mr. Mahesh Babu

Date of Birth : 01Jan 1988

Gender : Female

Languages known : English & Hindi

Hobbies : Listening music, reading books

Key strength : Positive thinking

Good Analytical & Non-Verbal skills

Creative

Team building

Contact this candidate