Engineer Design
Resume:
Michel Vercier
Chicago, IL 60642
********@*****.***
Highlights of Qualifications
Proven success in implementing state of the art systems and Hardware Design
Technical leadership skills and experience
Strong practical and theoretical foundation in systems and Hardware engineering
Professional Experience
Intel Wireless Group, Lake Zurich, IL May 2014-Present
Design Verification Engineer (Independent Contractor)
Verification of complex digital modem blocks (LTE) and sub-systems.
Execution of test plan, creation, simulation, debugging of tests
Simulation using VCS (DPI-C) and Virtex-7 FPGA
Texas Instruments, Schaumburg, IL May 2004-Mar. 2014
SoC Designer
Digital designer and lead in Mixed-signal organization. Involved in 8 digital designs for power
management and audio ICs ranging from 10kgates to more than 200kgates. Responsibilities
included team lead, interface with customers, system and analog teams, architecture of digital top,
RTL coding (VHDL and Verilog), lint checks (Spyglass), synthesis (Cadence RC), equivalence
checking (LEC), timing constraints and checks (STA), bug tracking, configuration management
(ClearCase). Provided support to verification team for RTL and Gate-level simulations. Evaluated
and provided feedback to digital design flow. Did some layout work for a small digital core.
Digital technical lead and architect of an ARM Cortex-M0 based power management circuit.
Integration lead for a 3G modem subsystem. Responsible for integration schedule (MS Project),
die size estimates, partitioning, RTL integration, lint, power management implementation and
checks (SpyGlass), configuration specs (ClearCase), formal verification (Verplex), bug tracking
(ClearQuest), ECO implementations (RTL, synthesis and post-layout netlist analysis, fix
identification, script implementation).
Integration lead for OMAP2420 ES2.0 and OMAP2640.
Co-chair of RTL/Synthesis/CTS track for 2007 and 2008 Physical Design RTL-to-PG symposia.
Professional Staffing Services, Algonquin, IL Apr. 2002-May 2004
Senior ASIC Engineer assigned to Texas Instruments
RTL integration of an ARM11-based OCP SoC (OMAP2420), ATPG, gate-level debugging
Porting and verification of testcases for OMAP1610 (ARM926, TMS320C55x).
Gate-level verification for OMAP1510.
Applied Micro Circuits Corporation, Downers Grove, IL Apr. 2001-Jan. 2002
Principal Engineer
Working on Facility Data Link receiver for DS1/E1 in a SONET framer with FIFO-based interface:
Architecture discussions, specifications, Verilog design, functional test strategy, Perl testbench for
verification.
Achievements:
Delivered specifications, HDL code, testbench and test scenario for FDL receiver by myself.
Very space efficient designed based on embedded RAMs.
3Com Corporation, Rolling Meadows, IL Jan. 1999-Mar. 2001
Senior ASIC Engineer
Working on wireless Ethernet (5 GHz) baseband: SPW simulation, architecture, HDL design.
Designed and coded in Verilog a behavioral model and a testbench environment for Gigabit
Ethernet receiver.
Participated in design reuse methodology and IP management (PCI cores, embedded
microprocessors).
Performed evaluation of formal verification tools (Formality, Design VERIFYer).
Project management class.
Achievements:
Delivered specifications, testbench and model for Gigabit Ethernet baseband receiver in two months.
Defined matrix for IP evaluation.
LSI Logic Corporation, Schaumburg, IL Dec. 1995-Jan. 1999
Field CoreWare Engineer
Specifications definition, design, simulation, VHDL coding, synthesis, implementation and timing
analysis of an adaptive equalizer for an HDTV ASIC demodulator.
Study of a demodulator for an MCNS cable modem.
Implementation of Reed-Solomon decoder, Interleaver and Descrambler for a cable modem ASIC.
Achievements:
Reduced by 50% the size of an adaptive equalizer for HDTV
Provided sales support
Modified design to meet customer needs and designed new ASIC in 3 months.
In-Flight Phone Corporation, Oakbrook Terrace, IL Mar. 1993-Dec. 1995
System Engineer
System Engineer for a European TDMA Terrestrial Flight Telephone System and an ISDN PBX
Cabin Telecommunications Unit.
Management of a 5 member team for flight tests with Lufthansa.
Attended ETSI specifications meetings.
Achievements:
Managed a project with foreign based vendor and customer
Ran first successful flight test of radio system for Europe
Alcatel Telspace, Cergy, France Mar. 1989-Feb. 1993
System Engineer
Responsible for an adaptive encoder-decoder for FLASH-TV.
Design of a 60,000 gate ASIC for satellite digital demodulation.
Study and implementation of digital techniques (filters, carrier recovery, synchronization, adaptive
equalization).
Design of a software simulator for digital satellite links.
Achievements:
ASIC from system design to layout and validation.
Development of a software platform for satellite communications
Education Bachelor of Science - Electronics Engineering - ENSEA, Cergy, France, 1989
Specialty: Signal Processing
Skills C/C++, Java, VBA, Unix, SPW, Matlab, VHDL, Verilog, Perl, Python, Tcl, synthesis
(Synopsys Design Compiler, Cadence RTL Compiler), formal verification (Formality, Verplex),
Design for Test (FastScan, Tetramax), Static Timing Analysis (PrimeTime, ETS), layout
(Cadence Vdio), configuration management (ClearCase, CVS), Vivado (Xilinx), Quartus
(Altera)
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