Project Test Cases

Kiran Sahu

Contact No.: +91-810******* E-Mail: **********@*****.***

Seeking a position in ASIC Design and Verification to enhance my knowledge and skills in technology development.

Professional Summary

A goal oriented and result driven individual with 3+ years of experience in Front End

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Design/Verification domain.

Worked on project for client on Verification of Graphics Processing Unit (GPU).

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Working knowledge of System Verilog, UVM and Verilog.

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Hands on experience in handling different tools NCSim, ModelSim, Xilinx ISE Project Navigator,

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VCS, Cadence Virtuoso

Other knowledge area –APB, AHB protocol, Computer architecture.

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Good team player with capacity to adopt new technologies and skills. Possess good written and verbal

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communication skills.

M. Tech (2011) in VLSI Design from National Institute of Technology, Nagpur(NIT Nagpur)

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Experience Summary

Employer Infosys Technologies Ltd.

Designation Verification Engineer

Experience From July 2011 – Till Date (3 years 7 month)

Skill-set

Hardware Description language: Verilog, System Verilog.

EDA Tools : ModelSim, VCS, NCSIM, Xilinx ISE Project Navigator,

Cadence Virtuoso, Eldo SPICE, Matlab.

Operating Systems : Linux, Windows, Unix.

Scripting : Perl

Software Languages : C++, C, Java

Scholastics

Degree/Exam University/Board Year CGPA/Percentage

M.Tech National Institute of Technology, Nagpur 2011 7.85

B.E. Bhilai Institute of Technology, Durg 2009 8.21

AISSCE M.G.M Senior Secondary School 2005 78.2%

AISSE M.G.M Senior Secondary School 2003 79.2%

Project Experience

Infosys Limited, Bangalore

Since July 2011, Systems Engineer

Project: Pre Silicon Validation

• Client: Intel

• Team consists of 20 members and this team is responsible for verification at unit, cluster and GT level.

• Role:

Improved my knowledge in C++, System Verilog for analysis of RTL code, AVM

methodology for writing error and display messages.

Regression testing at unit level.

Analysis of data flow through waveform, back tracing the signal for any undesired output

and debugging of the failing test cases by writing the dummy code in RTL and rerunning

regression.

Unit testing of functionality.

Coverage analysis of code and writing the test case for getting the required coverage.

Resolved ‘X’ propagation issues.

Verification of UART:

• Team consists of 6 members and this team is responsible for designing and verification of UART.

• Role:

Studied and improved my knowledge in Verilog and system Verilog used for verifying the

functionality of UART.

Developed the verification plan to test the UART model.

Built the APB transmitter and receiver reference model.

Developed the test cases for validation of control, data path and temporal functionality.

UVM Cadence Project:

The packet router has HBUS interface for programming register. It accepts data packets on single input

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port and routs the packets in multiple output channels.

• Role:

Developed stimulus model and simple sequences.

Explored UVM phases by writing few test cases.

Integrated the test bench and DUT using Virtual Interfaces.

Understood the system Verilog environment by integrating the developed UVC with

multiple UVCs.

APB Protocol Verification in UVM:

APB is a part of AMBA protocol family. It provides a low cost interface that is optimized for minimal

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power consumption and reduced interface complexity. The APB interfaces to any peripherals that are

low bandwidth and do not require the high performance of a pipelined bus interface.

• Role:

Developed a UVM based verification environment for APB protocol verification.

Developed the verification plans to test the APB model.

Created series of sequences and tests, to validate APB protocol.

AHB to Memory Bridge verification in UVM:

AHB is a new generation of AMBA bus which is intended to address the requirements of high

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performance synthesizable designs. It is a high performance system bus that supports multiple bus

masters and provides high bandwidth operation

• Role:

Worked on developing layered UVM test bench for verification of AHB protocol.

Developed the verification plans to test the features.

Writing the test cases and sequences with different control signals.

M.Tech Project: Design of low power processor for wireless sensor network

July 2010 2011

Summary: Basic design feature are low power design blocks specifically for the WSN node. The

block is hardware implemented to reduce the power consumption during data transmission from the

node. Sensor data is compressed using Haar wavelet.

Role : Some of the processor blocks are also designed and simulated in the current work. The

results for these blocks are as per the desired specifications. Design is synthesized for both FPGA and

ASIC. Xilinx XC2VP20 5FFL152 FPGA was chosen for synthesis. All simulations are done in Verilog

HDL. For, ASIC design, Synopsys Design Vision Tool is used to calculate hardware information and

power for compressor block.

Tool : Xilinx XC2VP20 5FFL152 FPGA, Synopsys Design Vision.

Scholastics Achievement

Secured 97.16 percentile in All India GATE exam year 2011.

Extramural Engagements

Attended Institute for Smart Structures and Systems (ISSS) National Conference on MEMS, Micro sensors,

Smart Materials structures and systems, VNIT Nagpur, 2010

Attended Mentor Forum for Verification event.

Personal Details

Date of Birth : 6 December 1987

Sex : Female

Father’s Name : Arjun Ram Sahu

Nationality : Indian

Linguistic Abilities : English, Hindi, Chattisgarhi

Marital Status : Married

Hobbies : Sudoku, Drawing, Cooking

Declaration

I hereby declare that the above written particulars are true to the best of my knowledge and belief.

Date:

Place:

Kiran Sahu

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