Engineer Design

Voonna Sandeep

Door no: *-*, Gajulavani veedhi, Kothavalasa, Contact no: +91-973*******

Vizianagaram district, Andhra Pradesh Email : *************@*****.***

OBJECTIVE

To be involved in work where I can utilize my skills effectively to contribute to the growth of

the organization.

EDUCATION

YEAR OF

DEGREE BOARD/UNIVERSITY C.G.P.A/PERCENTAGE PASSING

B.Tech

Indian Institute of Information

( electronics

C.G.P.A – 8.42

Technology

and 2013

(IIIT), Allahabad

communication

engineering )

Class- XII Board of intermediate education, A.P. 96.2% 2009

Class - X Board of secondary education, A.P. 88.83% 2007

TECHNICAL SKILLS

Operating systems: Windows 98/XP/Vista, UNIX

Tools, Libraries and Software: MS-Office, MATLAB7, Xilinx, cisco packet tracer

Programming Languages: Verilog, C, System Verilog, X86 Assembly language

Verification : UVM

Version control : CVS, GIT

RTL Synthesis tools : Design Compiler (DC)

RTL Simulators : VCS, QUESTASIM

AREAS OF INTEREST

Digital VLSI design

Data structures

Micro processors

WORK EXPERIENCE

Senior Software Engineer, Samsung R & D Institute, Bangalore June 2013 – Current

MVPU (Verification in UVM methodology)

Mobile vision processing unit is a complex SoC which involves multiple image processing blocks

required to support the applications like augmented reality, object tracking, 3D scan, emotion

recognition etc.

Currently working as verification engineer for Corner score block (corner detection) in MVPU

project.

Developed UVM environment for this block and currently closing the functional coverage for

the same.

Undergone required training for handling UVM and got understan ding on UVM verification flow.

Technologies and Tools Used: UVM, Questa-sim

SlimISP (ASIC design)

SlimISP is a block in Imaging Sub-system, involving crucial image processing algorithms,

which fits into the camera sensor pipeline between sensor to display.

Worked as a RTL Design Engineer for YCNR (Luma noise reduction and Chroma sub-sampling)

module which is highly Data path intensive and having challenging control path scenarios.

Developed C model and RTL Design for Color space conversion module in the same project

which is purely data path intensive.

Technologies and Tools Used: VCS, DC

ACADEMIC PROJECTS

Bandwidth-optimized Wideband Integrator (RTL design on FPGA)

Ngo’s digital integrator was remodeled with high speed adders and multipliers.

The proposed model exhibited 33% improvement in bandwidth over original model.

The results were published in IEEE NCCCS – 2012.

Platform/softwares: Xilinx, Spartan 3E FPGA, Matlab

FPGA Implementation of multiply-accumulator unit (RTL design on FPGA)

A MAC unit has been implemented digitally by choosing fast adders and multipliers required

for the design and optimized in terms of speed.

Platform/softwares: Xilinx, Spartan 3E

Laser based audio transmission

A transceiver circuit has been designed and implemented on PCB.

Platforms/softwares: Multisim, Ultiboard

ACADEMIC ACHIEVEMENTS

Done industrial training program at BHEL on the topic “STUDY OF PLC IN CNC MACHINES”.

Attended industrial training program at ALL INDIA RADIO (Visakhapatnam) on FM

transmission systems.

Secured 99.2 percentile in AIEEE-09 among 1,000,000 students who appeared for the test.

Secured 803 rank in EAMCET 2009 (A.P. state engineering entrance examination) and also

received a certificate of felicitation from AVOPA BANKMEN CHAPTER.

Secured 1656 rank in VITEEE-2009 (Vellore institute of technology engineering entrance

exam).

Secured 98.57 percentile in the quantitative section of eLitmus pH test.

EXTRA CURRICULAR AND ACHIEVEMENTS

Received Employee of the Month award in Jan-2015 @ Samsung R & D, Bangalore.

Won 2nd prize for solo dance competition in the cultural event held at Samsung.

Member of IHUMAN organization – Gajuwaka, A.P. formed to help the poor.

nd

Stood 2 in the chess competition held by GIPSA (Gajuwaka industrial sports association)

in 2009.

Recipient of Prathiba scholarship for all 4 years in the engineering college.

DECLARATION

I hereby declare that the above given information is true to the best of my knowledge.

Voonna Sandeep

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