Digital Design Verification, System verilog, UVM

SANDEEP V

Email: *******.************@*****.***

Mobile: +659******* +659*******

Objective

Seeking challenging and rewarding career opportunity in digital design verification

Experience

* *ears 6 months of experience in ASIC Front end. Involved Digital design, SoC

Verification, IP Verification, ARM Processor subsystem verification

Academic Details

MS in Microelectronics - 2012

University: BITS PILANI.

B E in electronics and communication - 2008

University: VTU.

Institution: BMS College of Engineering, Bangalore.

Skill Summary

In depth knowledge of Digital design and verification concepts

Possess strong experience in verification of several SoCs, ASICs, IPs and ARM

Processor based subsystems.

Possess strong experience in developing verification IPs using UVM.

Strong experience in System Verilog -

Functional coverage, Randomization, Assertions etc...

Possess strong experience using UVM Methodology for developing verification

Environment

Familiar in setting up environment and doing Gate Level simulations

Familiar with Synopsys and Cadence simulators and Tools

In depth knowledge in FPGA, STA, DFT, LINT, CDC etc...

Possess experience on UNIX, PERL scripting, Version control tools, Bug tracking

Tools

In depth Knowledge of Verilog, VHDL, C, C++, assembly etc...

Familiar with Protocols such as Ethernet, USB, CAN, I2C, UART, AXI, AHB,

APB, Camera Link, SPI etc...

Possess outstanding problem solving and debugging skills.

Professional Experience

FTDI CHIPS SINGAPORE (from Uniconnect) 2013 - Till date

FT900: SoC consists of a V3 processor core, Ethernet, USB, PWM, SD Card,

Camera, Debugger, CAN, I2C, UART, SPI, TIMERS, Interrupt Controller modules

Responsibility:

Perform verification of Ethernet, CAN and I2C Modules.

Responsible for developing Verification IPs for Ethernet, CAN and I2C protocol.

Responsible for implementing detailed Verification plan.

Responsible for developing Functional coverage and System Verilog Assertions.

Responsible for developing constrained random test cases, simulating,

Debugging and tracking them.

Assigned with responsibility of achieving 100% Functional and code coverage.

Responsible for helping junior in day to day work.

Duration: 4 months.

FT600: USB to FIFO converter - Bridge chip support USB3 Super speed and USB2

High speed and super speed, consisting of USB device controller, powerful

Processor, custom DMA controller, custom FIFO Master and Slave modules, I2C,

UART, Timer, SPI, GPIO and Interrupt Controller IPs

Responsibility:

Responsible for complete Verification of USB2 part of Device controller

Responsible for setting up verification environment in UVM

Take part in implementation of detailed Test plan for Verification

Responsible for identifying, implementing, simulating debugging and tracking of

Testcases

Responsible for Co-development of test cases in C language

Perform verification of IPs such as I2C, UART, Timer, Interrupt Controller, FIFO

Controllers

Responsible for developing constrained random test cases and functional

Coverage modules

Responsible for developing Functional Coverage and System Verilog Assertions

Responsible for providing support to design staff in debugging

Responsible for FPGA RTL and FPGA GATE simulations

Responsible for providing support to FPGA staff and Firmware staff

Assigned with responsibility of achieving 100% Functional and code coverage

Responsible for Gate level simulation

Development of camera link VIP model and verification of frame grabber module

Duration: 12 months.

LSI India R & D Pvt. Ltd (Avago) 2012 - 2013

Golden Eagle: SoC meant for networking application. Consists of quad ARM CA9

Core, ARM coresight components and several IPs

Responsibility:

Assigned with responsibility of verifying ARM Subsystem involving

CA9 and Coresight components

Assigned with responsibility of creating, modifying, simulating, debugging and

Tracking of tests against test plan

Assigned with responsibility of co-developing ARM assembly code

Responsible for supporting design staff in debugging

Performed verification of IPs at system level

Assigned with responsibility of developing functional coverage modules and

Achieving 100% functional and code coverage

Perform CA9 validation using ARM provide verification suite

Responsible for updating make scripts and analyzing reports for Spyglass Lint,

CDC and STA

Duration: 5 months.

Cheops: ARM Subsystem involving CR5 and CM0, designed to be part of

Consumer’s electronics

Responsibility:

Assigned with responsibility of verifying ARM Subsystem involving

CR5, CM0 and Coresight components

Assigned with responsibility of creating, modifying, running, debugging and

Tracking of tests against test plan

Assigned with responsibility of co-developing ARM assembly code

Responsible for supporting design staff in debugging

Responsible for simulating CR5 Cache and TCM integration validation suites

Responsible for ECCIP module Integration verification

Assigned with responsibility of achieving 100% code coverage

Perform tasks such as generating network interconnect using AMBA designer and

Generating memory modules

Perform validation of CR5 and CM0 using ARM provide verification suite

Duration: 5 months.

Stinger: ARM Subsystem involving CA9 and CR4, designed to be part of SoC

meant for hard disk drive controller.

Responsibility:

Assigned with responsibility of verifying ARM Subsystem involving CR4, CA9

And Coresight components

Responsible for developing top level test bench

Perform tasks such as generating network interconnect using AMBA designer and

Generating memory modules

Assigned responsibility of creating, modifying, running, debugging and tracking

Of tests against test plan

Assigned responsibility of co-developing ARM assembly code

Responsible for simulating CR4 Cache and TCM integration validation suites

Perform validation of ARM Processors using ARM provided validation suites

Assigned responsibility of achieving 100% code coverage

Attended internal training session for logic equivalence checking

Duration: 8 months.

Wipro Technologies 2008 - 2012:

Undergone training in Digital Design, Verification, STA, FPGA implementation,

System Verilog, UVM, Formal Incisive Verification, UNIX, scripting languages

Etc...

A/D Controller Macros and TIMER Macros: These IPs are designed to be part of

Renesas SoCs

Responsibility:

Involved in different versions of A/D Controllers and TIMER macros verification

Activity

Assigned with responsibility of developing test environment using UVM

Handled responsibility of creating, simulating, debugging and

Tracking of tests against test plan

Performed development of functional coverage modules and System Verilog

Assertions

Responsible for achieving 100% code coverage.

Assigned with responsibility of training and helping juniors in test case

Development

Functional coverage, Assertions etc.

Duration: 18 months.

USB2SATA Bridge: Bridge Chip was designed to enable hard disk drives with

SATA interfaces to connect with USB interface.

Responsibility:

Responsible for Top level Verification

Handled responsibility of creating, simulating, debugging and tracking of tests

Against test plan

Assigned with responsibility of developing System Verilog Assertions

Responsible for Code Coverage Analysis

Duration: 6 months.

FX4: Series of chips derived from Umbrella Chip for automotive application.

Responsibility:

Assigned with responsibility of updating test environment

Handled responsibility of updating, simulating, debugging and tracking of tests

Against test plan

Assigned with responsibility of developing System Verilog Assertions

Responsible for Code Coverage Analysis

Duration: 8months.

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