High School Design

RESUME

NAME : MD ZAFIR UDDIN

E-mail : *****.********@**********.***

Contact : +919*********

Objective:

Seeking a position of asic design&verification engg where fresh talent will add value to operations and

utilize my skills and abilities.

Profile Summary:

Good knowledge of digital,Verilog, system Verilog, uvm&ovm

Understanding of static timing analysis(STA)

Verification knowledge of systemverilog and uvm

Project details:

1. Ethernet packet loopback design verification using Systemverilog

2. AXI VIP Development using SystemVerilog

a. Description:

i. VIP component development for AXI3.0 protocol. As part of this project we

have developed BFM, Generator, Monitor, Coverage models. We have also

developed basic scenarios targeting all features of AXI protocol.

b. Tools used: Questasim

c. Responsibilities:

i. Developing VIP architecture

ii. Coding VIP components

iii. Validating AXI VIP using AXI slave model

3. Memory Controller Functional Verification using System Verilog

4. Uart using Verilog

5. AHB Interconnect Functional Verification using UVM & System Verilog

a. Description:

i. AHB interconnect is configurable design for connecting multiple masters to

multiple slaves. Design also has a configuration interface for configuring

slave address ranges. As part of design verification we verified interconnect

for different number of masters, slaves and slave address range

configurations.

b. Tools used: Questasim

c. Responsibilities:

i. Listing down features, scenarios

ii. Testplan development

iii. Developing testbench architecture

iv. Coding Testbench components including reference model and checkers

v. Verification closure using Functional coverage & code coverage as closing

criteria.

Technical Skills:

Programing language:- c,c++, Verilog, systemverilog,

pearl,

operating system:- linux, windows,Yosemite

eda tools:- questasim, cadence, modelsim

methodologies:- universal verification methodology(UVM)

protocol:- axi_vip, ahb

Professional Qualification:

B.Tech (Hons.), Electronics & Communication Engineering from “ADESH

INSTITUTE OF ENGINEERING & TECHNOLOGY, FARIDKOT” affiliated to “PTU,

JALANDHER” with an aggregate of 64%.

Educational Qualification:

Senior Secondary in Science, May 2008 (54%)

Marwari collage darbhanga bihar, affiliated to bseb Board.

Higher Secondary, May 2005 (55%)

Jawala mukhi high school darbhanga, affiliated to bseb Board

Personal Details:

Name: md zafir uddin Sex: Residence Phone: Mobile No.:

Male +919********* +919*********

Permanent Address: shastri park Near durga Email: *****.********@**********.***

mandir new delhi pin 110053

Present Address:madiwala btm 1st stage Marital Status: unmarried

venketeshwara layout Bangalore 560068

Date of Birth: 02/01/1989 Nationality: Indian

Other Skills:

Ability to work either alone or as part of a team (preferred).

Highly Motivated and Self starter who solves the problem with a business centric view.

Most Importantly, ability to learn and adapt quickly the new technologies and excellent technical,

analytical and problem solving skills.

Declaration:

I hereby declare that the information furnished above is true to the best of my knowledge and

belief.

(md zafir uddin)

Contact this candidate