Project Design
Resume:
Pavan Kumar Malka Ph: +1-571-***-****
*****.*****@*****.***
Career Overview:
An Engineering Professional with 5+ years of experience in ASIC Front end
flow
. Hardware Modeling,
. ASIC/FPGA Design, Verification, Synthesis
. Complex FPGA Implementations
. Design of Cryptographic modules and DSP hardware
Technical Skills:
Protocols : AMBA, JPEG2000, LTE, NAND flash, NOR Flash
Hardware Languages : System Verilog, VHDL, Verilog
Assertions : PSL, SVA
Programming Languages: C
Scripting Languages : Perl, Linux-Shell Scripting.
EDA Tools
Simulation : Cadence -NCSim, NC -Verilog, ModelSim, Synopsys-VCS,
Aldec - Active HDL
Lint Tools : Cadence -HAL
Synthesis : XILINX ISE, ALTERA- QUARTUS, Synopsys- Design Compiler
(DC)
Hardware Modelling : MATLAB, SCILAB, SIMULINK
STA : Altera TimeQuest Analyzer. Xilinx Trace
Operating system : Windows 7, XP, 2000, 98, and Linux environment
Repository Tools : CVS, SVN
Professional Experience Profile:
Staff Engineer
Xpectit Mobile Inc., USA
Jan 2014 - Present
Client : GE Healthcare
Project : Enhancement, Optimization and Verification of Legacy
Interface for MR
Tools Used : Altera - Quartus
Language : VHDL, Perl
Responsibilities:
Defining new functionality for optimum usage of the bandwidth of the
legacy interface
Optimizing the micro-architecture of the Interface for the new
functionality
RTL coding of the optimized part of the design and integrating with
the existing design of Interface
Test plan development for the verification of the IP
Synthesis using ALTERA - Quartus
Static Timing Analysis using Altera TimeQuest Analyzer
Client : GE Healthcare
Project : Enhancement of Verification Environment of PCIe Interface
devices of
MR Motherboard FPGA System
Tools Used : Modelsim, Altera - Quartus
Language : VHDL, Perl
Responsibilities:
Test plan enhancement for the verification of the system
Enhancing the Verification Environment
Enhancing the Checker and Monitor for self-checking capability of
the test bench
Writing new Test Cases for verifying the functionality of the
system
Client : Nuspay
Project : Optimization and Verification of AHB Interface IP
Tools Used : ModelSim, XILINX -ISE
Language : Verilog, System Verilog, Tcl, Perl
Responsibilities:
Optimizing the micro-architecture of AHB Bus Interface IP for speed
RTL coding of the optimized part of the design and integrating with
the existing design of AHB Bus Interface IP
Test plan development for the verification of the IP
Writing Reference Design in System Verilog for Unit-level
Verification
Creating Checker and Monitor for self-checking test bench & Writing
Test Cases for the IP
Creating Verification Environment & making the environment fully
automated
Creating Synthesis script and constraints file for XILINX ISE
Synthesis using XILINX ISE
Static Timing Analysis using Xilinx Trace and Gate level Timing
verification
Client : Nuspay
Project : Design and Verification of AHB-APB Bridge IP
Tools Used : ModelSim, XILINX -ISE
Language : Verilog, System Verilog, Tcl, Perl
Responsibilities:
Micro-architecture development of AHB-APB Bridge IP
RTL coding of the AHB-APB Bridge IP
Test plan development for the verification of the IP
Writing Reference Design of the IP in System Verilog for Unit-level
Verification
Creating Checker and Monitor & Writing Test Cases for the design
Creating Verification Environment & making the environment fully
automated
Creating Synthesis script and constraints file for XILINX ISE
Synthesis using XILINX ISE
Static Timing Analysis using Xilinx Trace and Gate level Timing
verification
Senior Engineer
Mindtree Ltd., India
Jul 2007 - Jun 2010
Project : LTE Frontend Passband Downlink Receiver
Tools Used : XILINX System Generator
Language : Verilog, Tcl
Platform : Custom
Responsibilities:
Study and understand the XILINX-System generator flow
Study LTE & Design RRC Filter, Interpolation Filter, IFFT, Mixer
using XILINX-System generator
Creating the verification environment for the Frontend Passband
Downlink Receiver IP
Integrating the IP with system & verifying the system
Created the synthesis scripts and constraints file for the IP
Project : FPGA Design & Validation of JPEG 2000 Encoder
Tools Used : VCS, NC-Verilog, ModelSim, XILINX- ISE, SCILAB
Language : Verilog, Tcl, Perl
Platform : ML 501
Responsibilities:
Architecture modeling of Data formatter, BPC Coding primitives
modules
Evaluating Data formatter and Bit Plane Coder (BPC) coding
primitive's module architecture using SCILAB by creating hardware
models
Micro-architecture development of Data formatter and BPC coding
primitives modules
RTL coding of the Data formatter and BPC coding primitives modules
Creating verification environment for Discrete Wavelet Transform
(DWT) and Data formatter, and for Bit Plane Coder (BPC) modules
Functional Verification and Gate level timing verification of the
modules
Creating Synthesis script and constraints file for JPEG2000 Encoder
IP for Xilinx
Validated the IP on ML501 board
Project : Design and Verification of APB Slave Bus Wrapper IP
Tools Used : VCS, NC-Verilog, ModelSim, XILINX- ISE, ALTERA-
Quartus
Language : Verilog, System Verilog, Perl
Platform : Custom
Responsibilities:
Micro-architecture development of APB Bus wrapper IP
RTL coding of the IP
Test plan development for the verification of the IP
Writing Reference Design in System Verilog for Unit-level
Verification
Creating System Verilog Verification Environment & making the
environment fully automated
Creating Checker and Monitor & Writing Test Cases for the design
Creating Synthesis scripts and constraints file for ALTERA -
Quartus, XILINX-ISE and Synopsys-Design Compiler
Synthesis using ALTERA -Quartus and XILINX ISE
Static Timing Analysis using Altera TimeQuest Analyzer and Xilinx
Trace and Gate level Timing verification
Project : Design of NOR Flash Controller IP
Tools Used : VCS, NC-Verilog, ModelSim, XILINX -ISE, ALTERA-
Quartus
Language : Verilog, Tcl
Platform : Custom
Responsibilities:
Micro-architecture development of NOR Flash Controller IP
RTL coding of the IP
Creating Synthesis scripts and constraints file for ALTERA -
Quartus, XILINX-ISE and Synopsys-Design Compiler
Synthesis using ALTERA -Quartus and XILINX ISE
Static Timing Analysis using Altera TimeQuest Analyzer and Xilinx
Trace and Gate level Timing verification
Project : Design of NAND Flash Controller IP
Tools Used : VCS, NC-Verilog, ModelSim, XILINX- ISE, ALTERA-
Quartus
Language : Verilog, Tcl
Platform : Custom
Responsibilities:
Micro-architecture development of NAND Flash Controller IP
RTL coding of the IP
Creating Synthesis scripts and constraints file for ALTERA -
Quartus, XILINX-ISE and Synopsys-Design Compiler
Synthesis using ALTERA -Quartus and XILINX ISE
Static Timing Analysis using Altera TimeQuest Analyzer and Xilinx
Trace and Gate level Timing verification
Project : Design of System Controller IP
Tools Used : VCS, NC-Verilog, ModelSim, XILINX- ISE, ALTERA-
Quartus
Language : Verilog, Tcl
Platform : Custom
Responsibilities:.
Micro-architecture development of System Controller IP
RTL coding of the IP
Creating Synthesis scripts and constraints file for ALTERA -
Quartus, XILINX-ISE and Synopsys-Design Compiler
Synthesis using ALTERA -Quartus and XILINX ISE
Static Timing Analysis using Altera TimeQuest Analyzer and Xilinx
Trace and Gate level Timing verification
Project : Design of On Chip Memory Controller (OCMC) IP
Tools Used : VCS, NC-Verilog, ModelSim, XILINX ISE, ALTERA- Quartus
Language : Verilog, Tcl
Platform : Custom
Responsibilities:.
Micro-architecture development of OCMC IP
RTL coding of the IP
Creating Synthesis scripts and constraints file for ALTERA -
Quartus, XILINX-ISE and Synopsys-Design Compiler
Synthesis using ALTERA -Quartus and XILINX ISE
Static Timing Analysis using Altera TimeQuest Analyzer and Xilinx
Trace and Gate level Timing verification
Project : Design of AHB Bus Controller IP
Tools Used : VCS, NC-Verilog, ModelSim, XILINX- ISE, ALTERA-
Quartus
Language : Verilog, Tcl
Platform : Custom
Responsibilities:
Micro-architecture development of AHB Bus Controller IP
RTL coding of the IP
Creating Synthesis scripts and constraints file for ALTERA -
Quartus, XILINX-ISE and Synopsys-Design Compiler
Synthesis using ALTERA -Quartus and XILINX ISE
Static Timing Analysis using Altera TimeQuest Analyzer and Xilinx
Trace and Gate level Timing verification
Project : Design of Pulse Width Modulation IP
Tools Used : VCS, NC-Verilog, ModelSim, XILINX ISE, ALTERA- Quartus
Language : Verilog, Tcl, Perl
Platform : Custom
Responsibilities:
Micro-architecture development of PWM IP
RTL coding of the PWM IP
Created verification environment for PWM IP in Verilog
Creating Checker and Monitor & Writing Test Cases for the design
Creating Synthesis scripts and constraints file for ALTERA -
Quartus, XILINX-ISE and Synopsys-Design Compiler
Synthesis using ALTERA -Quartus and XILINX ISE
Static Timing Analysis using Altera TimeQuest Analyzer and Xilinx
Trace and Gate level Timing verification
Project : Design of AHB Slave Bus Wrapper IP
Tools Used : VCS, NC-Verilog, ModelSim, XILINX -ISE, ALTERA-
Quartus
Language : Verilog, Tcl
Platform : Custom
Responsibilities:
Micro-architecture development of AHB Wrapper IP
RTL coding of the IP
Creating Synthesis scripts and constraints file for ALTERA -
Quartus, XILINX-ISE and Synopsys-Design Compiler
Synthesis using ALTERA -Quartus and XILINX ISE
Static Timing Analysis using Altera TimeQuest Analyzer and Xilinx
Trace and Gate level Timing verification
Verification Engineer
Infoserv India, India
Aug 2006 - Jun 2007
Project : Verification of Source GEN interface.
Tools Used : ModelSim.
Language : Verilog, Perl
Responsibilities:
Development of Bus Function Modules. (BFM) Source GEN Interface
using Verilog
Test plan development of the unit under verification
Writing Checker in Verilog & Writing Test Cases for the unit
Creating Verification Environment and making the environment fully
automated
Master Student
George Mason University, USA
Aug 2011 - May 2013
Project : Hardware Implementation of Channel Estimation in LTE Downlink
Tools Used : Aldec- Active HDL, ModelSim, XILINX- ISE, ALTERA -
Quartus,
GMU - ATHENa, MATLAB
Language : VHDL
Responsibilities:
. Architecture modeling using MATLAB
. Micro-architecture development of Area efficient Channel Estimation
Hardware module
. Micro-architecture development of Fast Convolution Method based
Channel Estimation Module
. RTL coding of the designed modules
. Creating verification environment for both the design modules
. Functional Verification of the modules
. Synthesis of modules using XILINX ISE
. Static Timing Analysis using Xilinx Trace and Gate level Timing
verification
. Evaluating the throughput to area ratio using GMU's evaluation
platform ATHENa
Project : 3D Hybrid DRAM Performance, Temperature and Power Analysis
Tools Used : Temperature Analysis -HotSpot, Power Analysis - DRAMsim2
Language : Perl
Responsibilities:
. Study the literature pertaining to proposed architecture
. Analysis of literature and tools required for the proposed
architecture
. Floorplan creation for the processor and, DRAM for various
configurations of the architecture
. Simulation and analysis of test results
Project : FPGA Design & Verification of Galois/Counter Mode (GCM)
Tools Used : Aldec- Active HDL, ModelSim, XILINX -ISE, ALTERA -
Quartus,
GMU - ATHENa.
Language : VHDL
Responsibilities:
. Micro-architecture development of AES algorithm
. Micro-architecture development of GCM module
. RTL coding of the AES algorithm and GCM modules
. Creating verification environment for AES algorithm and GCM modules
. Functional Testing and Verification of modules
. Synthesis of AES and GCM modules using XILINX ISE
. Static Timing Analysis using Xilinx Trace and Gate level Timing
verification
. Evaluating the throughput to area ratio using GMU's evaluation
platform ATHENa
Project : FPGA Design & Verification of PHOTON Hash Function
Tools Used : Aldec-Active HDL, ModelSim, XILINX- ISE
Language : VHDL
Responsibilities:
. Micro-architecture development - Datapath and Controller
. RTL coding of the Datapath and Controller modules
. Creating verification environment for the design
. Functional Verification and gate level timing verification of modules
. Synthesis using Xilinx ISE
. Static Timing Analysis using Xilinx Trace
Educational Profile:
MS in Computer Engineering from George Mason University, VA, USA
Advanced Post Graduate Diploma in VLSI from VEDANT, SCL India, Mohali,
India
Bachelor of Engineering in Electronics & Communication from V.T.U,
Karnataka, India
Accomplishments:
. As a leading member of the new design team, designed generic, re-
usable and, scalable IP's for unique SoC (System on Chip) for easy
integration of custom modules and, to reduce time-to-market for the
products
. Created high-quality AHB based SoC eco-system designs and doubled the
IP portfolio of Mindtree within 15 months of creation of new team
. Worked as a stall presenter for MindTree Ltd- services group's stall in
MindTree Tech Fest 2008
& Presented paper on "Hardware Modelling Flow" in MindTree Tech Fest
2009
. FPGA design of PHOTON Hash function secured 2nd prize in Course level
design contest in
George Mason University
Training:
. Attended and, cleared Altera worldwide certification program in 2008
. Cleared Japanese Language Proficiency Test level 4 in 2008
Reference:
Will be provided on request
Pavan Kumar .M
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