Design Engineer
Resume:
RESUME
SHEELA B PATIL
Email: **********@*****.***
Mobile: +91-819*******
PROFILE:
2+ years of experience in VLSI domain, hands on experience in system
verilog and UVM worked mainly on Router 1x3,SPI master controller, AHBtoAPB
IP core verification,UART verification. Had 1.5 years of experience as
digital and analog layout engineer in KarMic.
PROFESSIONAL EXPERIENCE:
Staff Intern,Maven Silicon
Working on Front end design and Verification.
Good understanding of the ASIC design flow.
Experience in writing RTL models in Verilog HDL and Testbenches in System
Verilog and UVM.
Experience in using industry standard EDA tools for front-end design and
verification.
Experience in System Verilog, UVM methodology and Perl.
1.5 experience in KarMic Design Center as Design and Layout Engineer
Work Experience in System verilog.
Hands on experience in Cadence Virtuoso 180 nm technologies.
Analog Layouts (Floor planning, block level checks (DRC/LVS)).
Digital Layouts (Building standard cell library,AOI,cells)
TECHNICAL SKILLS:
HDL: Verilog
HVL: SystemVerilog
Verification Methodologies: Coverage Driven Verification
Assertion Based Verification - SVA
TB Methodology: UVM
Protocols: SPI,AMBA(AHB,APB),UART
EDA Tool: Questasim and ISE,Cadence Virtuoso
Domain: ASIC/FPGA front-end Design and
Verification
Knowledge: RTL Coding, FSM based design, Simulation,
Code Coverage, Functional
Coverage, Synthesis,
Static Timing Analysis, ABV-
SVA
Layout tools: Cadence virtuoso layout editor,TSMC-
Magic,Questasim.
DESIGN AND VERIFICATION PROJECTS:
1. Router 1x3 - RTL design and Verification:
HDL: Verilog
HVL: SystemVerilog
TB Methodology: UVM
EDA Tools: Questasim and ISE
Description: The router accepts data packets on a single 8-bit port and
routes them to one of the three output channels, channel0, channel1 and
channel2.
Responsibilities:
Architected the design
Implemented RTL using Verilog HDL.
Architected the class based verification environment using system Verilog
Verified the RTL model using SystemVerilog.
Generated functional and code coverage for the RTL verification sign-off
Synthesized the design
2. SPI Controller Core - Verification:
HVL: SystemVerilog
TB Methodology: UVM
EDA Tools: Questasim
Description: The SPI IP core provides serial communication capabilities
with variable length of transfer word. This core can be configured to
connect with 8 slaves.
Responsibilities:
Architected the class based verification environment in UVM
Verified the RTL module using System Verilog
Generated functional and code coverage for the RTL verification sign-off
3. PCS(Ethernet) -RTL design:
HVL: Verilog
EDA Tool: Questasim
Description: Designed the Physical Coding Sublayer that comprises of
Transmitter(Encoder),Receiver(Decoder,Synchronizer),Auto Negotiation block.
Responsibilities:
Architected the design
Implemented RTL using Verilog HDL
4. AHB2APB Bridge IP Core Verification:
HVL: System Verilog
TB Methodology: UVM
EDA Tool: Questasim
Description: The AHB to APB bridge is an AHB slave which works as an
interface between the high speed AHB and the low performance APB buses
Responsibilities:
Architected the class based verification environment in UVM
Verified the RTL module with single master and single slave
Generated functional and code coverage for the RTL verification sign-off
BASIC VLSI TRAINING
Client : Karmic Training Centre, Manipal.
Description:
MOS theory- MOSFET construction, working, fabrication.
Basic circuit analysis, Digital and Analog modules.
Analog and Mixed mode layout issues.
LT-SPICE, NGSPICE simulations.
Overview of ASIC physical design.
TESTER ON CHIP (MEMORY) - 350nm Technology
Client : Karmic Training Centre, Manipal.
Team Size : 5
Development/Productivity Tool : Magic VLSI tool.
Description and Responsibilities :
Worked on layout of SRAM cell, Modeling of Memory Controller block using
Verilog language.
Worked on digital layouts of STANDARD CELLin Magic 350nm VLSI tool.
The project aims at testing digital IC's for their correctness in their
operation.
Understanding of key features to be taken care of in digital layout
designs.
Understanding Memory SRAM one bit cell, Decoders in Memory part of TOC
EDUCATION SUMMERY:
Degree / Board Institute Major and Percentag
Course and Specialization e
Date
Bachelor of Visvesvaraya SKSVMACET, Electronics and 78
Engineering Technological Laxmeshwar Communication
University.
Pre Karnataka State P.C JABIN PU P,C,M,B 76
University Pre-University College,
(PUC), 2008 Board. Hubli
SSLC, 2006 Karnataka State N.K.THAKKAR EMHS, NA 89.28
Board. Hubli
PROFESSIONAL QUALIFICATION:
Maven Silicon Certified Advanced VLSI Design and Verification course
from Maven Silicon VLSI Design and Training Center, Bangalore
PERSONAL DETAILS:
Father : BASANAGOUDA
Mother: UMA
Date of Birth: 16-06-1990
Languages Known: Kannada, English and Hindi.
DECLARATION:
I here by declare that all the details furnished above are true to the best
of my knowledge.
Place: Bangalore
SHEELA B PATIL
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