Engineer Electrical

Kenneth Woods

** ****** **

Westford, Ma ********.692.0763

< ***********@*******.*** >

Professional Summary

. Demonstrated ability to identify and solve difficult problems.

Tenacious problem solver.

. Top Down design including HDL synthesis and verification, as well as

Test & ROOT cause failure analysis. Designed

Intel_Itanium_Architecture (IA64) board model and signal integrity

solution

. Extensive embedded microprocessor designs: PPC860, MIPs, and Motorola

COLDFIRE

. Experienced integrating Real Time Operating System (RTOS) and In

Circuit Emulators(BDM-ICE) development

. Design and layout of PCI_Mezzanine_Card(PMC) and Compact PCI bus(CPCI)

and PCIx VPN card

. Designed, tested, and received Agency approval for production of

Telecom repeater, fault Tolerant

Skills / Tools

. RTL design, since first job: Microcode firmware for airborne

computers, classified (U) ASPJ Sanders Associates. Classified (U)

S3B Microcode firmware for phased array sonar. Sanders Associates.

. Further, VHDL & Verilog, as well as FPGAs work is / are implicitly

RTL; however, they also incorporate synthesis & simulation (Modelsim)

verification.

. DSP training course at Raytheon, board level design at Envoy Networks.

. FPGAs XILINX reference designs Simulink & Matlab through NU Horizons

training.

. VERILOG & VHDL code, synthesis and simulation/verification. Cadence,

signal integrity & Spectraquest timing driven layout, ORCAD,

Simplicity, Model Technology, Viewlogic (EPD2004).

. Backpanel design and signal integrity experience. Mixed Analog and

Digital environments.

. Solved 30% failure of VPN card with 100% yield thru knowledge and

SPICE simulation of PLL filter and magnetics.

. FPGA experience: XILINX, ALTERA, and also VLSI training, and ASIC

verification.

. Datacom experience: designed 10/100 Gigabit Ethernet switch.

. Designed, tested, and received Agency approval for production of

Telecom repeater, fault tolerant.

. Board level Phase Lock Loop expertise, SMT ferrites SRF, and high

speed decoupling. Low ESR & ESL.

. Knowledge of Agency Standards and PCB emission and isolation PCB

layout techniques.

. Signal Integrity design and analysis, Mathcad field solver software

and analysis tools "XFLUX".

. Cadence's Allegro PCB layout tool. HF board material selection and

stackup, Spice modeling of PCB stackup.

. Test Equipment using Oscilloscope, Logic Analyzers & Spectrum

Analyzers, PCB TDR, and jitter analysis.

. Experience with telecom signaling for digital, analog and mixed

signaling hardware. 50Mhz precision analog modem test.

. Agency tested and approved dual protected DS3/E3 repeater card and

backplane (Tautron/Inrange telecom, fiber optic and equalization of

long & attenuated distorted copper signals.

. Familiar with OrCAD Capture, Cadence Allegro Spectra schematic capture

and or Spectra constraint driven PCB layout tools (at Celestica and

Nortel).

. Mentor_EPD (Goodrich_Survillance) Viewlogic (Raytheon), as well as

Altium/Protel schematic & PCB autorouter.

. Ability to write and debug structured programs to automate functional

testing. Raytheon C# training, test vector port from Mentor &

Textronix production into verification and reconciliation of

discrepancies reported to Navy FBM program office. See 26 ASICs, dozen

circuit cards, and mixed mode backplane.

. National Instruments (NI) TestStand. C# and CPP, since Raytheon.

Embedded C FPGA Small Device C Compiler (SDCC), Labview & NI training

at Nu Horizons with Xilinx ISE development.

. JTAG at Intrinsix, FPGA, HDL (VHDL & Verilog), timing simulation

Raytheon, Examples, Viewlogic/Mentor EPD2000, XILINX ISE,

Altera/Quartus, as well as Actel Designer.

. Documentation and Analysis 1000 page Trident Guidance Computer

delivered to Navy FBM.

. Test & Verification, Top_Down Methodology training and Root Cause

Failure analysis since Raytheon.

Professional Experience:

DIAGNOSYS LLC, through ENTEGEE, Lowell, Mass.

10/2011 - 02/2012

PCB LAYOUT & ENGINEERING Orders, SCHEMATICS using ALTIUM, & PCB Layout

PROTEL.

NumiaMedical, through Lighthouse Placement, Lyndonville, Vt.

10/2009 - 3/2010

Principal Electrical Engineer

. Design and develop second generation precision infusion pumps using

Altium (Protel) SCH & PCB Layout tools. Designed low voltage Motor

Control Ckt ( 2.5_amp), as well as identified/corrected RF issues, Flex

interconnect. PIC Embedded Motor Control design using 18F8722, and VHDL

update to CPLD, using Xilinx ISE & ModelsimXE

Passport Systems, through National Engineering, Billerica, MA

9/2009 - 10/2009

Senior Engineer

. Border Sensor System, Homeland Security using ORCAD schematics and SPICE

simulation. Hi Voltage Detector, low ripple, Rad hard wiring

implementation,

. Analyzed and recommended differential implementation, Supported

Design_Review & found mechanical flaws. Designed and tested signaling

hardware for digital, analog, and mixed signaling hardware.

Christie Digital, through Oxford International

8/2008 - 10/2008

Senior Engineer

. PCIEx16 backplane for Cinema HD projectors, TI Digital Light

Projector(DLP)

. Based upon signal integrity experience, selected high signal count

differential Mictor

. Generated symbol, and 17 pages of schematics. Entered design review

Kollmorgen EO (Electro_Optical ), through Patriot Technical, Billerica, MA

3/2008 - 5/2008

Senior Electrical Engineer

. Embedded Processor FPGA Control Logic. Ship mast_/_periscope optical.

. Concept requirements & pseudo-code, schematics, thru VHDL coding,

synthesis & test. Application: Periscope MAST RS485 serial interface &

SPI flash reprogramming downlink. System design implemented thru

complete XILINX AppNotes, translated voluminous requirements

specification 10k lines to psueducode text. Implemented dual 1Mhz

RS232 serial links using low cost SPARTAN3AN FPGA eval platform bench

test.

Teradyne, Design & Debug Current Mode Clock Jitter & Distribution

9/2007 - 1/2008

Senior Electrical Engineer

. Teradyne : 3rd generation Hi Speed multiple 3Ghz Backplane, 200Mhz

Source Synchronous, low jitter and low skew, current mode isolation

and distribution, Generated specification and completed design &

review. My research identified signal integrity concerns of Altera

Stratix_2GX family, which Dr. Howard Johnson cited up to 300mv current

mode differential (error) whereas, for which Xilinx family had

improved Vrail & GND pattern. However, other (prior design core)

sister project testing ultimately revealed that the Stratix_2GX

implementation flawed thru IBM IP because 3Gig serial links Clock &

Data Recovery (CDR) initial settings detection and adjustment were not

capable of maintaining loss of lock and sync over noise and

temperature drift. Altera Stratix_IIGx_FPGA resync_PLL_Interface.

ECRM, Tewsbury, Upgrade FPGAs, Debug & Test and corrected noise flaws

2/2007 - 6/2007

. ECRM: Violet Photo processing machines, 22_FPGA Respins & Retest.

. Further, identified & corrected three Board designs susceptible to

FPGA buffer noise Simultaneous_Switching_Outputs (SSO) which resulted

from high switching speeds, GND_bounce, crosstalk, and active_hi

signals.

Prima Laser : Tested CAN_Bus interface with USB Logic Analyzer, Software

flaw 8/2006 - 10/2006

Senior Engineer

. Prima Laser (through Summit Technical) High Voltage Power Supply FPGA

controller HDL synthesis & Modelsim Simulation,

. Industrial CO2 Laser: Test prototype, Analyze Noise & Communication

Errors Can Buss & USB logic Analyzer.

Boston Engineering, through Oxford International

2/2006 - 3/2006

Senior Engineer

. Precision Modem test set : ANALOG High precision 0.1% 0.1dB Modem Test

Interface flat thru 50_Mhz :

. Current Feedback Op Amp design, w/Spice analysis, based upon my prior

experience with equalization through 1/5Ghz at Tautron Inrange

(Copper_/_Fiber_Optic)

ICAD (Computer Aided Cancer Detection) 9/2005

- 1/2006

Senior Engineer

. Computer Aided Cancer Detection) Medical Film Imaging Scanner

. Critical Noise reduction and image enhancement retrofit thru FPGA

Sum_to_Memory over 8 images.

. VHDL coding & Compiler synthesis of ISE6 versus ISE7 compiler issues,

and simulate Sum to Memory through embedded RAM Virtex_2.

Goodrich Surveillance & Reconnaissance System (SRS)

9/2003 - 6/2005

Senior Engineer

. Test Engineer and FPGA designer. Test Fibre Channel Video & IR, Test

multi board FPGA and FIFO imaging enhancement features, repair, and

root cause failure analysis of image processing boards including Fibre

optic transmitter, receiver, and Phase Locked Loop (PLL). Ultimately,

failure of MAC aggravated by undervoltage, noise, and temperature.

. FPGA design of VME interface including board symbols, circuit, parts

list, generate test vectors to validate FPGA design and board circuit.

XILINX, and Viewlogic (MENTOR EPD2004) schematics, VHDL, EDIF, and

board review. Support Test and integration of verification engineer.

Generate performance specification.

Celestica, through Adecco

10/2001 - 1/2002

Senior Engineer

. Intel Itanium (IA-64) High speed Spectra Timing Driven layout, DDR

Signal_ Integrity.

. Performed research & analysis to design 800_Mhz Source Synchronous

Scalability bus for Intel Itanium server IA-64.

. Cadence CONCEPT schematic capture, and PSPICE modeling & simulation.

. Identify critical design parameters and generate performance

specification.

. Intel Itaniam IA-64 Server: 400_Mhz Trinary LVDS_/_CML buss.

. Performed PCB design for AGTL+/LVDS and researched advanced PCB design

considerations and materials including characteristic impedance,

Stackup, Crosstalk, Impedance: Spice modeling of traces, and crosstalk

management.

. Impedance Modeled and considered reasonably priced materials including

Getek's MERLYN, and Nelco_4000 & 6000.

. Cadence Constraint driven timing_/_rules driven PCB layout & training

(Spectra).

Envoy Networks, Burlington 3/2001

- 8/2001

Senior Engineer

. Hardware Engineer. Wireless CDMA Network design of System Controller

ATM_IMA and Timebase controller utilizing Rubidium Oscillator module.

. PLL and LVDS distribution. ORCAD schematic capture and Allegro PCB

tool. Application: Telecom RF timebase controller for 3G wireless.

Nortel, Billerica, through RCM Technologies

6/2000 - 2/2001

Senior Hardware Engineer

. I tested the failure lot of worst twenty boards from Nortel's

production run, and was able to identify and resolve failures through

demonstrated rework and subsequently design respin.

. Failure lot of thirty boards fixed respins, entirely producible

without defect.

. Packet Edge board level redesign of T1/E1 network card, ATM_IMA, PLL

expertise, PADS circuit board layout of mezanine card, Compact_PCI

(CPCI) and Mezzanine(PMC) board level design system design and debug.

. PSPICE and Viewlogic schematic capture.

. Debug of WindRiver Real Time Software (RTOS) through PLX9054 PCI

bridge and FIFO queue.

. Integration and test of Network Encryption and cipher/compression

circuit card.

. Corrected real time operating system software error created by time

compression through FIFO hardware. REAL TIME OS and WIND RIVER IN

CIRCUIT EMULATOR (Backround_Debug_Mode (BDM).

XIOX (@COM, when dot com names were fashionable) 3/1999

- 5/2000

Senior Hardware Engineer

. Schematic design of a multiport 10/100 Ethernet/GBE card, FPGA, and

embedded processor MIPs IDT 32364 & 4640/4650.

. Generate Performance specification of multiport Gigabit Ethernet board

and implement design Viewdraw: AMD cancelled production run GBE 10/100

multiport.

. Write Verilog HDL/HVL VERIFICATION code FPGA synthesized using

Synplicity, routed using Altera Max Plus, and simulated and verified

using Model Technology.

INRANGE TECHNOLOGIES/TAUTRON, Westford, MA, 10/1997 -

3/1999

Senior Engineer

. Designed dual 10/100 Ethernet controller board with embedded, COLDFIRE

5307 processor, AM79C973 Altera_FPGA, PLX_9054 PCI Bridge, FLASH,

SynchDRAM, and DC_Converters.

. Generated performance specification thru schematics. Stewart

integrated 10/100 magnetics 3_volt and '973 PHY.

. Designed Coldfire based microcontroller and 120vdc isolated milliamp

current sensor. Utilized low ripple high voltage DC converter, and

isolated precision A/D converter. BOM, testplan, and performed

circuit board test and integration.

. Telecom STS-1/DS3 Switchable Repeater board, Acquired knowledge of

Agency Standards and testing. Received Qualification/Approval.

. In order to accomplish this design, I determined that a high

sensitivity compensating op-amp design was required for optimal

performance/operation across 1500_ft coax at -35_dB attenuation.

. As part of this discrete ANALOG design I performed SPICE simulations

and bench testing/tuning of circuit configuration and performance

analysis of components versus SPICE results.

. Generated performance specification, schematics of circuit board and

backplane.

. Performed integration and test verification of this design down to

single bit error detection (1E-23) across process (Industrial

Environmental, voltage, and noise/frequency/JITTER).

. Prototype volume ten, Production volume hundred.

. Communications & Telecom: Performed research of SONET, SDH & CORE_499

standards regarding Performance Monitor(PM) of SONET versus SDH, and

found otherwise unknown options within PMC Sierra chipset.

INTRINSIX (Contractor), Westborough, MA, ASIC/FPGA Design (Teradyne)

5/1995 - 6/1997

Senior Electrical Engineer

. VME bus master/slave interface using Actel FPGAs, VME bus model design

and simulation on Viewlogic UNIX and PC platforms.

. Cadence board level schematic. Integration of controller board into

Teradyne test systems. This design included synthesis of "reverse

engineered" AMD device "PL141 VHDL & ROM. "MICROCONTROLLER" which had

been discontinued by AMD.

. This allowed Teradyne to salvage IP based upon object code, vastly

extending the production life and reducing the cost of all such PL141

microcontroller board level designs.

. Full industrial design and fabrication process and design environment

Estimated Teradyne production volume in the hundreds.

. ASIC consolidation of multiple Xilinx FPGAs using EXEMPLAR.

Interstate Technical Services, Nashua, NH Senior Design (Sanders/Lockheed)

9/1994 - 4/1995

Senior electrical engineer. Contractor: European Space Satellite

. Actel FPGA schematic design and simulation with VIEWlogic schematic

and simulation using ACTEL

timing designer. 3000 & 4000 series; Problematic due to faulty ACTEL

Designer schematic macros.

Raytheon, Marlborough, MA. Senior Design Engineer,

11/1997 - 8/1994

(Computer Design Department VLSI & Ckt_Card Design Group). Federal

Ballistic Missile (FBM) program.

Visiting scientist to CSDL

. Designed, fabricated, tested ultra-quiet analog & digital mixed signal

backplane for Guidance system.

FBM Laboratory: Verification of Digital & Analog circuits using

Oscilloscopes & Logic Analyzers.

. Performed simulation, timing and verification analysis of Guidance

Computer multiprocessor system.

. Technical writing description, two volumes, 1200 pages.

. Optics imaging and Charge Coupled Device (CCD) analysis, redesign of

image processing system and circuit.

. VLSI gate level modeling, simulation, and verification on the

VIEWlogic and VHDL behavioral modeling.

. Design verification and reconciliation between Mentor/VIEWlogic

simulation EDIF translation from MENTOR into VIEWlogic circuits of 20

modules and 18 VLSI designs, generate and translation of test vectors.

G&S Systems (MIT Spinoff), Naval Warfare Emulation Systems

4/1983 - 10/1987

. Responsible for the design and development of emulation electronics

circuit cards & firmware including an intelligent NTDS DMA controller

and proprietary Processor-Bus interface.

. These Embedded systems were subcontracted to Raytheon and delivered to

IBM Federal Systems for "Submarine_Advanced_Combat_SYSTEMS (SUBACS),

Submarine peripheral electronics and weapons emulation.

. Emulation systems were also sold to the Naval Underwater Systems

Center (NUSC) and delivery was also made to Sperry as a frigate

trainer for the Spanish Navy. volume 20. 68000 IN CIRCUIT EMULATOR:

APPLIED MICROSYSTEMS

Sanders Associates, Nashua, NH, Design Engineer, Electronic Warfare

6/1979 - 3/1983

. Responsible for board level design of 68000 based controller, and

performed detailed circuit design and test of board & instruction

sets, as well as microcode/firmware in order to implement the

following embedded computers: RTL design: Microcode firmware 110 bits

implementing airborne computers, Airborne Self Protect Jammer( ASPJ).

. S3B Microcode firmware for phased array sonar computer 1750 ISA,

ANUYK20 ISA.

. Advanced Systems Countermeasures, Electronic

Countermeasures/Electronic Warfare experience: Responsible for

microcode development of the ATAC-16M computer.

. The ATAC computer was the Air Force standard computer prior to the

1750.

. The ATAC was required for use by the Airborne Self Protect Jammer

(ASPJ) electronic warfare countermeasures suite.

Solar Power Corp./Exxon, Technician, Test and evaluate efficiency

optimization of panels and arrays.

Education:

. Paralegal Certificate, Northern Essex Community College, Haverhill, MA

1/2003 - 1/2007

. Postgraduate Electrical Engineering - Computer Science

1/1981 - 8/1983

Northeastern University & ULowell.

. B.S. Electrical Engineering, Magna Cum Laude, University of

Massachusetts, Lowell, MA.

Professional Training:

. VHDL Design Course - Northeastern University.

. Optics graduate course UMass Lowell.

. Analog, Digital, and Mixed Mode Design/Simulation - VIEWlogic course

Indianapolis.

. UNIX, KALMAN filters, Sonar Course, and DSP course -Raytheon.

. IEEE Radar Course: Raytheon, Wayland. Eli Brookner,

. Pascal and Data Structures and Techniques - Sanders Associates

Formal education & training: DSP training: Raytheon, DSP training VLSI

course, IEEE radar, VLSI: Raytheon

VHDL Northeastern University, Signal_Integrity, Top_Down_Design

(to_Verification_standard), System_Verilog

GBE Verification GBE & RMII, XIOX: Manchester, NH

Formal ASIC & multiple FPGA HVL Hardware Verification & ASIC signoff.

Training: Linux, Netware Admin, Visual_C, System_C synthesis & embedded,

XILINX, Burlington, spring 2009.

RTL design, since first job: Microcode firmware for airborne

computers, classified (U) ASPJ Sanders Associates. classified (U)

S3B Microcode firmware for phased array sonar. Sanders Associates.

Further, VHDL & Verilog, as well as FPGAs work is / are implicitly RTL;

however, they also incorporate synthesis & simulation (Modelsim)

verification.

DSP training course at Raytheon, board level design at Envoy Networks.

FPGA reference designs Sanders Associates.

FPGAs XILINX reference designs Simulink & Matlab through NU Horizons

training.

Contact this candidate