VLSI Verification
Resume:
BIPIN KUMAR VERMA
EH-**, Sector E, Deen Dayal Nagar, Bhind Road, Gwalior-474020,M.P.
Email:************@*****.*** Contact: +918*********
OBJECTIVE
To be a part of well established, progressive, professionally managed organization which could provide me
an adequate opportunity to draw upon my knowledge, experience & clear strengths to the mutual benefits to
the organization as well as for me.
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PROFILE
•
Having 1 yearof experience in Verification Domain.
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Good understanding of ASIC verification flow.
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Good programming skills in SystemVerilog and Verilog.
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Good understanding and programming skills using Universal Verification Methodologies UVM.
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Hands on experience with EDA tools (Questasim, Cadence Virtuoso).
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Understanding of functional coverage metric and identification of additional scenarios.
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Good understanding and designing of circuits in Cadence Virtuoso.
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• Experience of developing the verification environment using System Verilog and industry standard
verification methodologies(UVM).
TECHNICAL SKILLS
Category Tools/Languages
HDL Verilog.
HVL System Verilog.
Methodology UVM
Design Environment Cadence Virtuoso.
Debugging Tools ModelSIM v10.0d, Questasim 10.2c,
Synthesis Tools Xilinx ISE 13.1
C, C++
Programming languages
EDUCATIONAL CREDENTIALS
Year of
Examination Board/University School/Institute CGPA/Marks Passing
10th Standard CBSE K.V.No.2 2005 61.2
12th Standard CBSE K.V.No.2 2007 61.0
BE(EC) RGTU(Bhopal) SRCEM,Gwalior 2011 72.38
M. Tech (VLSI Design) ITMU (Gwalior) ITMU, Gwalior 2013 8.43
PUBLICATIONS
Title Enhanced ground bounce noise reduction in a low-leakage CMOS multiplier.
1.
Journal International Journal Of Electronics, Taylor & Francis.
Status Published.
Date 06-Dec-2014.
Title Ground bounce noise reduction aware combinational multi threshold CMOS circuits
2.
for nanoscale CMOS multiplier.
Journal Frontiers of Optoelectronics, Springer.
Status Published.
Date 14-Aug-2014.
Title Lowering Ground Bounce Noise in Tri-Mode MTCMOS Circuits with Threshold
3.
Voltage Tuning.
Journal African Journal of Computing & ICTs (IEEE Nigeria Section).
Status Published.
Date 01-Sep-2014.
Title Enhanced reduction of ground bounce noise in low leakage CMOS multiplier with
4.
combinational MTCMOS circuit.
Conference IEEE International Conference on Signal Processing, Computing and Control
(ISPCC) 2013.
Status Published.
Date 26-Sep-2013.
PROJECTS UNDERTAKEN
1. Title Design of Finger Print Recognition System.
Period Working.
Location Bengaluru(KA).
Technologies Verilog, UVM.
Abstract Project entailed designing of Finger Print Recognition system in Verilog. The
extraction of minutiae points from the sample fingerprint images and then
performing fingerprint matching.
2. Title Design of Fast Fourier Transform (FFT).
Period 2 months.
Location Bengaluru(KA).
Technologies Verilog.
Abstract Project entailed designing of 8x8 FFT hardware software partition with respect to
implementation on microcontroller and FPGA.
3. Title Design and Verification of Physical Layer USB3.0.
Period 5 months.
Locaton Bengaluru(KA).
Technologies Verilog, System Verilog, UVM.
Abstract Project entailed design of the working of Physical layer of USB 3.0 in Verilog and
verification in UVM. It implements the transfer of scrambled and encoded data in the
DC balanced values from transmitter and unscrambling and decoding at receiver end.
4. Title Design and Verification of Random-access Memory (RAM).
Period 3 months.
Location Bengaluru(KA).
Technologies Verilog, System Verilog.
Abstract Project entailed design of RAM in verilog and verification in system verilog. It
allows data items to be read and written in roughly the same amount of time
regardless of the order in which data items are accessed.
5. Title Study of Avionics System of Light Combat Aircraft (LCA).
Period 1 month.
Location Bengaluru(KA).
Abstract Project entailed study on avionics system of HAL Tejas aircraft. Tejas aircraft is an
indigenous aircraft equipped with Glass Cockpit, INSGPS (Inertial Navigation
Systems and Global Positioning System) and Fly by Wire System.
6. Title Design of Micro-strip Patch Antenna.
Period 4 months.
Location Gwalior(MP).
Technologies IE3D, Mentor Graphics.
Abstract Project entailed design of narrowband, wide-beam patch antenna. They are mounted
on the exterior of aircraft and spacecraft, or are incorporated into mobile radio
communications devices.
WORK EXPERINCE
Job Title: Trainee VLSI Design.
1.
Company: GLOBALS RESEARCH INNOVATION & DEVELOPMENT, Bengaluru.
Duration: March 2014 to till date.
EXTRA-CURRICULAR ACTIVITIES
• Participated in National Level workshop – 2011 ‘Digital System & VLSI Design’ (ITM Universe,
Gwalior).
• Participated in Tech-Fests – 2010 ‘Robot Arm’ (IIT Roorkee).
• Participated in Technovation –2009 ‘Robotics’ (SRCEM, Gwalior).
• Participated in Participate in ‘Boston science quiz 2006’.
• Participated in ‘National Science Olympiad & Science Model Competition 2005’.
LANGUAGE KNOWN
• English, Hindi.
PERSONAL PROFILE
Father’s Name: ` Sri. Nand Lal Verma
Date of Birth: 05 Sep 1990
Nationality: Indian
Permanent Address: C/O Lallan Prasad Verma
Vill. – Gopalpur
PO – Baragaon
Dist. – Varanasi (U.P.), Pin – 221204
DECLARATION
I hereby declare that all the above information is true to the best of my knowledge & belief.
(BIPIN KUMAR VERMA)
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