Project Design

RESUME

VISHWANAT MUDDI

"SAMSKRUTI" *th cross

Sri Ramanagar

Ranebennur -581115

Dist. Haveri

E-mail:

***************@*****.***

Contact: +91-994*******

CAREER OBJECTIVE:

A responsible and challenging position that will allow me to explore my

abilities and skills and sense of dedication towards my duties with a aim

of seeing the progress of the organisation and to adapt to the changing

organisation needs with changing global scenario.

EDUCATION QUALIFICATION:

Course Board/ School/ Year of Percentage

University College Passing

M.Tech in VLSI VTU Belgum BVBCET HUBLI 2014 83.42

DESIGN & TESTING

B.E. in VTU S.T.J.I.T. 2012 64.57

Electronics & Belgaum Ranebennur.

Communications

DIPLOMA in DTE Bangalore K.H.Kabbur Inst of 2008 63.75

Electronics & Engineering Dharwad

Communications

Class X Karnataka Dr:B.R.Ambedkar High 2005 69.44

state School

secondary Ranebennur

education

TECHNICAL PROFICIENCY:

> SOFTWARE LANGUAGES : C, Assembly level language 8051/ARM7

> HARDWARE LANGUAGES : VHDL, Verilog.

> TOOLS WORKED : Xilinx, Cadance, Spice, Eagle, Mat Lab,

LABVIEW, Keil, and LaTex.

> AREA OF INTEREST : CMOS VLSI,Analog & Mixed Mode VLSI.

> OPERATING SYSTEM : Linux

LIST OF PUBLICATIONS:

Conference:

1. "Comparison of Phase Frequency Detectors by Different Logic Gates and

Implementation of Charge Pump," NCET 2K14 GEC Ponda-Goa pp 52-57,

Apr 2014.

2. "A High Speed, Low Power Consumption D Flip-Flop for High Speed Phase

Frequency Detector and Frequency Divider" ICCTEM Mysore, Karnataka,

pp. 700-705, July-2014.

Journals:

1. "Design and Implementation of Phase Locked Loop using Current Starved

Voltage Controlled Oscillator in GPDK 90 nm," International Journal of

Ethics in Engineering & Management Education ISSN: 2348-4748, pp. 41-

46 Volume 1, Issue 6, June 2014.

2. "A High Speed, Low Power Consumption D Flip-Flop for High Speed Phase

Frequency Detector and Frequency Divider," International Journal of

Electronics and Communication Engineering & Technology (IJECET) ISSN:

0976-6464 pp. 185-193 Volume 5, Issue 8, August 2014.

WORKSHOP ATTENDED:

. Attend 15 days workshop on "WORKSHOP TO ENHANCE THE PLACEMENT

ACTIVITIES FOR PG STUDENTS" in BVBCET Hubli.

. Attend 3 days workshop on "Process Improvement through Analysis using

Simulation" in BVBCET Hubli.

. Attend 1 day workshop on "PCB Design using CADDO-71" in BVBCET Hubli.

PROJECT PROFILE

Major Project (During 4th SEM)

Title: Design and Implementation of Phase Locked Loop using Current Starved

Voltage Controlled Ocsillator in gpdk 90 nm.

Tools: CADANCE

Description: This projects focus on design of High-Speed, Low Power

Consumption, faster face and frequency locking PLL. Here a current starved

ring oscillator has been considered for its superior performance in form of

its low chip area, low power consumption and wide tuneable frequency

range.All micsellious blocks of PLL had been designed in GPDK 90nm CMOS

Technology with supply voltage 1.8V using CADENCE spectre tool. Virtuoso

Analog Design Environment tool of Cadence have used to design and simulate

schematic. Different types of simulations are carried out in the Spectre

simulator.VCO and overall integration of PLL Simulations were done for all

process corners (NN,SS,SF,FS,FF) and temperature (-40?C to +100?c).

Different expressions was calculated by using calculator. Layout was done

for voltage controlled oscillator and frequency divider.

Minor Project (During 3rd SEM)

Title: A High-Speed, Low Power Consumption Positive Edge Triggered D Flip-

Flop for High Speed Phase Frequency Detector in 180 nm CMOS Technology.

Tools: CADANCE

Description: The design of conventional and proposed D Flip-Flop was

considered and its transistor level design was obtained. The schematic was

laid in Cadence tool and a Transient analysis was done.

Mini Project (During 3rd SEM)

Title: Comparison of Phase Frequency Detector using different logic gates

and Implementation of Charge pump.

Tools: CADANCE

Description: The design of Phase Frequency Detector using different logic

gates and Implementation of Charge pump and its transistor level design was

obtained. The schematic was laid in Cadence tool and a Transient analysis

was done.

COURSE PROJECT IN M.TECH

Project #1(During 1st SEM)

Title: Design of CMOS logic circuit with layout of a Boolean expression and

optimize the ordering of poly gates in layout by appropriate methods.

Tools: CADENCE

Project #2(During 1st SEM)

Title: Application to Generate Knight Rider Pattern on the LEDs Given in

the MBED Tools: KEIL

Project #3(During 1st SEM)

Title: 8-Point FFT sProcessor Tools: Xilinx

Project #4(During 2nd SEM)

Title: Design of Flip flops and Latches for low power Tools: NGspice for

simulation

Project #5(During 2nd SEM)

Title: Built In Self Test (BIST) Tools: Xilinx

Project #6(During 2nd SEM)

Title: N-bit Linear Feed Back Register (LFSR) Tools: Xilinx

Final Year Project in Bachelor of Engineering

Title: "IDENTIFICATION AND CLASSIFICATION OF CROPS"

Members: 04

Description: Automatic detection of crops is an essential as it may prove

benefits in monitoring large fields of crops, and thus automatically detect

the crops. Therefore, looking for fast, automatic, less expensive and

accurate method to detect crops is of great realistic significance. The

color feature is used to recognize and classify different agriculture crops

using MATLAB.

Tools: MATLAB

EXTRA CURRICULAR:

. Organize the workshop for juniors in M.Tech.

. Class Representative in final year of M.Tech.

. Had volunteered in college workshop.

. Partcipated in technical event [ppt's].

. Involved in Social Activity.

PERSONAL PROFILE:

Name : Vishwanath Muddi.

Father's Name : Mruthyunjay Muddi.

Mother's Name : Sushila Muddi.

Nationality : Indian

Date of Birth : 5th Jul 1989

Hobbies : Collecting system utilities, browsing

internet, cooking.

Languages Known : English, Hindi and Kannada.

Declaration:

I declare that the information given above is true to the best of my

knowledge.

DATE :

PLACE : Ranebennur

(vishwanath)

Contact this candidate