Design Electrical Engineering

RAHUL RAVI KUMAR

*** ***** ******, ***. **. **, San Jose, California - 95126 +1-716-***-**** ********@*******.***

http://www.rahulravikumar.com https://www.linkedin.com/in/rahulravikumar

EDUCATION

University at Buffalo, The State University of New York Concentration: Very Large Scale Integration-VLSI

Master of Science, Electrical Engineering, December 2014 GPA: 3.7/4.0

BNM Institute of Technology, Visveswaraya Technological University

Bachelor of Engineering, Electronics and Communication Engineering, June 2013

TECHNICAL SKILLS

Software Languages: C C++ Verilog VHDL Python

Hardware: ARM Cortex M-3 Land Tiger (LPC 1768) PIC 16F 8051 Microcontroller Basys2 FPGA

Software: Cadence Virtuoso Spectre Keil uVision Xilinx ISE ModelSim Matlab Microsoft Office Network Simulator-3

COURSEWORK

Introduction to VLSI HDL Based Digital Design Computer Architecture Fundamentals of Modern VLSI Analog Integrated

Circuit Layout Analog Circuits Microelectromechanical Systems Microelectronic Device Fabrication Embedded Systems

and Applications Principles of Networking Consumer Optoelectronics

PROJECTS

16-bit RISC Processor, Spring 2014

• Design and simulation of sequential and combinational building blocks of non-pipelined RISC processors.

• Designed MIPS ISA consisting of 16 instructions consisting ALU, Memory Load/Store and control instructions.

• Simulation of results is performed by giving test patterns in Xilinx

Tool used: Xilinx ISE HDL Language: Verilog

Chip Multi Threaded Processor, Spring 2014

• Designed a reduced MIPS ISA Chip Multi-Threaded processor with 4 Fine-grained threads, which are issued in round-

robin fashion using a rotating priority resolver.

• Incorporated Non-Blocking Cache and Miss Status Handling Register (MSHR) to emulate instruction and data cache

misses

Tool used: Xilinx ISE HDL Language: VHDL

Random Number Adder, Spring 2014

• Design of a circuit generating two 5-bit random numbers using LFSR and then adds them.

• Displayed the result on the seven-segment display of the Basys2 FPGA board.

Tool used: Xilinx ISE HDL Language: Verilog Hardware: Basys2 FPGA

64-bit Memory cell using Sleepy SRAM, Fall 2013

• Executed power gating methods by controlling sub-threshold current using sleep transistors.

• Design of Sense Amplifiers, Pre charge Circuit, Row Decoder and Read/Write Circuit.

• 25% Power reduction observed when compared with 6T SRAM in AMI-06 process.

Tool used: Cadence Virtuoso Simulation: SPECTRE

Design of a Two-Stage Op Amp, Fall 2014

• The Op Amp was designed for TSMC25 technology and Level 1 Spice Model.

• RC Miller circuit was employed as a frequency compensation technique to improve the Phase Margin.

• Tuned the circuit to obtain a gain of Av > 77.5dB, Phase Margin > 60deg, Gain Bandwidth = 10MHz.

Tool used: Cadence Virtuoso Simulation: SPECTRE

Linear Voltage Regulator Circuit, Spring 2014

• Design and Layout of a Series Linear Voltage Regulator in AMI-16 process.

• Implemented layout techniques such as common centroid, matching, shielding and the use of dummy devices.

• Inter-digitizing all the modules has reduced the effects of mismatch.

Tool used: Cadence Virtuoso Simulation: SPECTRE

Digital Multi-Media Player, Fall 2013

Implemented multimedia player on ARM Cortex M3 microcontroller with Keil uVision software to integrate multiple

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source codes.

Created an interactive interface for the user to choose between Image viewer, MP3 player and gaming menu using

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joystick present on the board.

Tool Used: Keil uVision Programming Language: Embedded C Hardware: Land Tiger LPC1768 board

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