Design Project

ARPANA JANE LAWRENCE

“ARUNODHAYAM”,

*/*, **. ************ ******,

Redfields, Coimbatore-641045

Email : *************@*****.***

Mobile: +91-774*******, +91-948*******

Career Objective

To be a part of an organization of repute wherein I would be able to work in challenging

projects to contribute and learn as a team.

Education

M.Tech(VLSI design): currently pursuing at joint collaboration of CDAC_ACTS,

Pune and Veltech University,8.89 CGPA.(2015)

BE (Electronics and Communication Engineering): Dr. Mahalingam College of

Engineering and Technology, 8.5 CGPA (2013)

Higher Secondary: St. Joseph’s matriculation higher secondary school,

93.7% (2009)

High School: St. Joseph’s matriculation higher secondary school, 89%

(2007)

Projects

“FPGA prototyping for vehicle trajectory display” using zed board.

Project description:

This project focuses on providing guidelines for the drivers during reverse parking.

Efficient techniques are used so that the memory consumed is less and hence can be

implemented in lower end cars.

“FPGA” Implementation of Fool-proof encoder and decoder using LDPC codes

- using Xilinx ISim simulator(Spartan 3)

Project description:

This project focuses on the achieving a fully fault-tolerant memory system that is

capable of tolerating errors both in the memory also all the other supporting logic including

the encoders and decoders. Euclidean Geometry low density parity check codes were used.

Design of vga controller using verilog HDL(virtex 4)

Custom design using cadence:

Circuit design,Simulation,Layout design and testing of standard cells

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Design of adder using 28,32 and 14 transistors.

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Area of Interest

Digital design

RTL coding

ASIC

Languages and software known

Verilog HDL

VHDL

Cadence virtuoso

Training

Indian Institute of VLSI design and training on custom digital design & layout

using cadence EDA tools for a duration of one month.

Hands -on-training on Digital IC Design –using Cadence EDA for 1 day

Undergone in-plant training at SALZER ELECTRONICS, Coimbatore, for one week.

Undergone training at Bharat Sanchar Nigam Limited, Coimbatore for one week.

Extra-Curricular Activities

Joint secretary of WIE (women in IEEE)– (2011-2012)

Treasurer of WIE – (2012-2013)

Active member of “ELIXER”(MUSIC CLUB)

Achievements

Have secured Prime Minister, Government of India’s scholarship for securing above

90% in the 12 examination among children of Indian Armed Forces

Have secured Indian Naval Benevolent Association Scholarship

Received Certificate of Merit and Cash Award from Member, Secretary of Finance,

Ministry of Finance Welfare Fund.

Industrial Visits

Indian Telecommunication Industries, Kanjikode, Palghat

Kerala Electronics Ltd, Kochi.

Personal Details

Father’s Name : ANTONY LAWRENCE

Mother’s Name : VASANTHA LAWRENCE

Date of Birth : 27.09.1991

Nationality : Indian

Languages known : English, Hindi, Tamil and Malayalam

Hobbies : Dancing, Singing and Drawing

Passport number : L9149863

Declaration

I hereby declare that all the particulars of information and facts stated above are true,

correct and complete to the best of my knowledge and belief.

PLACE: Coimbatore ARPANA JANE LAWRENCE

DATE:

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