Design Engineer

Khossrow Assadi

CAPABILITIES

Specification, functional design, verification and analysis of ASICs and FPGAs

Experienced with satellite communications such as BUS1553 and Spacewire

FPGA expertise with design, constraint creation, and place-and-route and error

analysis and resolution.

Space based Worst Case analysis, EMI/EMC analysis, Thermal analysis, FPGA SEU

analysis, Electrical transient analysis. Risk mitigation techniques. FPGA safe

recovery mechanism and SW tradeoffs.

Board level power integrity and signal integrity.

Space-based image acquisition.

EXPERIENCE

Parker Aerospace (March 2013- June 2013)

Performed DO-254 configuration management and traceability compliance process for FPGA

design and implementation for fly-by-wire avionics. Created/modified DO-254-10.00 section

documents using DOORS software. Used MKS tool for configuration management, problem

reporting, analysis and resolution of FPGA requirement errors. Created FPGA checklists for

documents based on DO-254.

Gurley Instruments Corp (July2012-October2012)

Performed VHDL code coverage and verification of the optical encoder/decoder FPGA interface

to a SPI TX/RX block. Created System Verilog Assertions to achieve code coverage goals.

Verified the valdity of the FPGA simulation test cases.

Lockheed Martin Space System Senior Member Technical Staff, Hardware Engineering, 2001-

2012. Projects:

• Space-based Advanced Sterling Radio Isotope Generator (ASRG) power supply

Performed worst-case, thermal, radiation, signal integrity, power integrity and EMI analysis on

the controller board housekeeping FPGA. Ensured immunity of the FPGA functions from any

SEU and electrical transients.

• Space-based X-Ray Instrument

Developed low-power FPGA requirement-driven design, simulation, and synthesis. Work

included schematics, part selection, thermal analysis, pre-layout PSpice, and Hyperlynx

simulation. Used Simulink to create test benches for the telemetry channels.

• GeoEye Imaging Satellite

Developed uplink/downlink specification and FPGA requirement-driven design, simulation, and

synthesis. Used Mentor Graphic HDL Designer to comply with DO-254 FPGA coding rules and

FAA Design Assurance Processes for the uplink and downlink receiver and transmitter FPGA.

Used EPDM and DOORS for requirements traceability.

•

• Geostationary Lightning Mapper (GOES-R weather satellite)

Responsible for creating requirements and specifications for a flight FPGA. Designed logic and

performed synthesis for Xilinx FPGA. Applied DO-254 VHDL code compliance rules and

NASA processes. Designed and implemented Manchester encoder/decoder serial

communication. Designed using low noise techniques to acquire high speed data from a large

Focal Plane Array. Using Xilinx internal features the preprocessed pixels were transmitted via

serdes IOs to the host

• Demonstration Payload Program for Space (LADAR)

Design and verification of a flight Actel FPGA running at 250 MHz for transmission and

reception of LADAR data. Used System Verilog Assertions to verify the FPGA requirements.

• Special Program

Design and layout of Xilinx FPGA adaptor used for prototyping and ASIC verification of three

types of flight PWBs. Developed RTL code to interface to serial LVDS backplane of special-

purpose DSP IP. Verified the design through simulation and assertions. Employed Xilinx EDK

and System Generator using Simulink Xilinx blocks to implement certain VHDL blocks.

• Risk Mitigation

Design and layout of high-speed board to risk-mitigate Spacewire IP core and LVDS physical

interface using Xilinx FPGA. Created RTL code to interface PPC to IP core, running at

200Mbits/sec. Evaluated signal quality and eye patterns driving a 15m loopback cable.

Developed LVDS standards for Lockheed Martin Space System

• HARDENED RISK PROCESSOR ASIC

Participated in a 700K gate, radiation-hardened, proprietary RISC processor ASIC design.

Activities included:

Functional simulation and verification

Synthesis using Synopsys DC compiler

Constraints scripts

Gate-level simulation

POST-LAYOUT VERIFICATION AND STATIC TIMING ANALYSIS

Ciena Corporation, Senior Hardware Engineer, 1998 to 2001

Design and development of an optical Quad OC12 line cards. Tasks included layout and

fabrication. Debug board. Designed RTL code for Xilinx FPGA to interface with front-end

SONET ASIC to serial backplane driver ASIC chips. Data was at 622Mbits/sec per channel

using LVDS FPGA IO speed.

FPGA DESIGN TOOLS and Devices

Xilinx Virtx(power pc) series, Actel RTAX and Flash series, Altera

Simulink-Modelsim co-simulation

Xilinx ISE, System Generator and Actel Libero

Questa and Modelsim simulators and Synplify synthesis

System Verilog Assertions

Mentor Graphic Formal for logic debug and analysis

Mentor Graphic 0in Clock Domain Crossing (CDC) analysis

Board Design Tools

Orcad and Mentor Graphic capture

PSPICE, Hyperlynx simulation

EDUCATION

M.S. and B.S. Electrical Engineering, Magna cum Laude, University of Utah

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