NAVEEN KUMAR MADALA
***************@*****.*** +91-707*******
Objective:
To work in a globally competitive environment on challenging
assignments that shall yield the twin benefits of the job satisfaction
and a steady pace professional growth.
Education:
> M.Tech in Gokaraju Rangaraju Institute Of Engineering And Technology
> B.Tech from MallaReddy Engineering College
> Higher Secondary from Sri Sai Junior College
> Secondary from APRS Kodigenahalli
Skill Set:
Design Tools : Xilinx ISE
Software Languages : C, C++, Oops
HDL : Verilog
HDVL : System Verilog
Methodologies : OVM, UVM
Circuit Simulators : Questasim
Scripting Languages : Perl, Python
Editors : Vim
Versioning Systems : CVS and SVN
Academic projects:
Video Watermarking Based On Region Information Of Motion
Vectors
The main objective is to increase embedding strength of every
block in the video sequence to maximum value, to improve
imperceptibility of the watermarking and achieve excellent robustness
and security. The imperceptibility of proposed method is measured by
calculating PSNR of the video watermarked videos with different
embedding control parameter, by getting the average value of the PSNR
of every frame of the video
Design and implementation of DDR3 controller with AXI
compliant
The AXI compliant DDR Controller permits the access of DDR
memory through AXI Bus interface. The DDR controller works as an
important bridge between the AXI host and DDR memory. It takes care of
the DDR initialization and various timing requirements of the DDR
memory. The Design has been implemented in Verilog and verification is
done in systemverilog.
Personal Details:
Correspondence : S/o M.C.Sanjeeva Rayudu,
D.No:6-5-201, H.No:305,
S.S.Towers, Ram Nagar Main Road, Ram Nagar,
Anantapur,
Andhra Pradesh.
Date of Birth : April 15 1989
Marital Status : Single
Languages Known : Telugu, Hindi, English
Declaration:
I hereby affirm that all the details provided above are
true to the best of my knowledge.