Design Engineer Engineering

VEERAMALLU GOWTAM RAJ KUMAR

Gajjaram(post),

Tallapudi Mandal,

Contact No: +918*********

West Godavari District,

Email ID: *******.**********@*****.***

Andhra pradesh, PIN:534341.

Career Objective

Being a VLSI Design Engineer, I am looking for the position of a Digital Design Engineer that

requires applying of my technical knowledge and analytical skills in the field of VLSI as well as

give a good support to my team and organization.

Academics

• Pursuing M.Tech (VLSI Design, 2013-2015) at VNR Vignana Jyothi Institute of Engineering and

Technology with 86.5% in first year.

• Completed B.Tech (ECE, 2008-2012) at Sri Prakash College of Engineering affiliated to JNTU,

Kakinada with an aggregate of 76.15%.

• Completed Intermediate (2008) at SVD Junior College, Rajahmundry with an aggregate of 87%.

• Completed SSC (2006) at Hamsavahini School, Tallapudi with 84.33%.

Technical Skills

• Knowledge on : Digital,VLSI,CMOS basics

• Languages : C,Verilog,VHDL

• Tools :

Front End: ModelSim, Xilinx,VCS, Design Compiler, Formality, Design Architect

Back End: Mentor Tools, Custom Design in Synopsys, IC Process

Strengths

• Good Communication Skills

• Hard Working

• Flexible

• Positive Attitude

Extracurricular Activities

• Member of .Sri Prakash Blood club.

• Departmental level organized an event SPUTNIK.

Co-curricular Activities

• Presented a technical paper titled Optical Camouflage at GITE college,Rajahmundry.

• Organized many events in schooling level.

• Qualified in GATE 2013 with a Gate Score of 490 and a rank of 11000.

Projects

1.Title

BARREL SHIFTER.

:

Role

Design of Schematic And Layout (Backend).

:

Organization

VNR VJIET.

:

Description

Draw the Schematic and Layout for shifter and performing DRC and LVS.

:

Tools Mentor Graphics (Design Architect and IC Process).

Used :

2.Title

Design of Direct Form FIR Filter with coefficients +1 or -1.

:

Role

Designing a Verilog code (Frontend).

:

Organization

VNR VJIET.

:

Description Write an Verilog code for the design using +1 coefficient and observe the

: simulation results of the FIR filter.

Tools Modelsim.

Used :

Skills

3.Title

Design of 4-bit Up-Down Counter.

:

Role

Designing a counter.

:

Organization

VNR VJIET.

:

Description

Write an Verilog code, Simulate and checking the design report of a counter.

:

Tools Synopsys Design Compiler.

Used :

Personal Details

Name : V. Gowtam raj kumar

Age : 23

Date of Birth : 1991, july 09

Father name : V. Satya Sai

Languages Known : Telugu, English

Declaration

I here by declare that all the information mentioned above is true to the best of my knowledge.

Place: Hyderabad Signature

(V.GOWTAM RAJ KUMAR)

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