Design Engineering

KAI DU

**** *. ***** ***. *** *, Los Angeles, CA, 90007

**********@*****.*** 323-***-****

EDUCATION

Master of Science, Electrical Engineering (MSEE), GPA: 3.57

2013.8 - 2015.5

University of Southern California (USC), Los Angeles, CA

Emphasis: VLSI circuit design

Bachelor of Engineering, Electrical Engineering and Automation, GPA: 91/100

2008.9 - 2012.7

Beijing Institute of Petrochemical Technology, Beijing, China

Emphasis: Circuit design

TECHNICAL SKILLS

Programming languages: Verilog HDL, VHDL, Perl, C++, C, Assembly Language

Applications: Modelsim, Simvision, Design Complier, PrimeTime, Conformal,

Encounter, Cadence Virtuoso, Keil C51, Quartus, Protel, Matlab,

Proteus, AutoCAD

ACADEMIC PROJECTS

Design of DDR2 memory controller [Verilog, Primetime, Design Compiler,

Encounter] 2014.10 - 2014.11

1. Interfaced with testbench and Denali memory module, including FIFOs,

processing logic and ring buffer, and supporting reading, writing and

refreshing, etc.

2. Programmed in Verilog, verified by SimVision, PrimeTime and Conformal,

synthesized by Design Compiler, and implemented Placement & Routing by

Encounter.

Implementation of CPU with Tomasulo algorithm [VHDL, ModelSim, Xilinx ISE]

2014.7 - 2014.8

1. Programmed in VHDL, and ModelSim was used to verify the functionality.

2. Implemented a CPU with out-of-order execution and in-order dispatch

and completion. Branch prediction buffer, reorder buffer (ROB), CFC,

FRL, PRF were all separately designed. Synthesized the design on

Spartan-6 FPGA.

Implementation of a 5-stage pipelined CPU [Verilog HDL, ModelSim]

2013.10

1. Designed in Verilog, simulated by ModelSim, implemented based on early

branch structure with data-stationary control, including forwarding

and stalling units to handle data and control hazards.

Design of 1K SRAM [Cadence Virtuoso, Perl]

2014.2

1. Used 6T SRAM cell, including pre-charging circuit, row and column

decoders, and sense amplifier.

2. Implemented in 0.18?m technology and performed extracted-model

simulations in Cadence Virtuoso. DRC & LVS cleared.

Design of a general purpose microprocessor [Cadence Virtuoso, Perl]

2014.4 - 2014.5

1. Designed a full-custom processor in transistor level which supports

general MIPS instruction set, containing ALU, main memory, and

controlling logic.

2. Optimized the delay based on logic effort and power dissipation by

clock gating.

3. Cadence Virtuoso was used to implement the schematic and layout. Perl

script was chosen to decode commands and test the functionality.

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