Project Data

ABDUL SAJID SHAIK

Email: *****.****@*****.*** Address for communication:

**/*, *** *****, ******** Extn,

Contact No: +91-991*******

Date Of Birth: 01-May-1991 Old Post Off. Rd, Madiwala,

Bangalore - 68

OBJECTIVE:

To seek a challenging career in VLSI, where my knowledge and technical skills will

improve my career growth while enabling the organization to achieve its’ targets.

ACADEMIC PROFILE:

Name of the Year Percentage/

Qualification Board/University

Institution of Passing CGPA

M.Tech in Sathyabama Institute

(Very Large Scale of Science and Sathyabama

2014 8.19

Integrated Technology, University

Circuit Design) Chennai.

B. Tech in Sri Kalahasteeswara Jawaharlal Nehru

(Electronics and Institute of Technological

2012 70.47

Communications Technology, University,

Engineering) Srikalahasti. Anantapur.

Sri Siddhartha Junior Board of

Intermediate

College, Intermediate, 2008 92.9

(M.P.C)

Srikalahasti. Andhra Pradesh

Sri Swami

Board of Secondary

Vivekananda High

S.S.C Education, 2006 79.16

School,

Andhra Pradesh

Srikalahasti.

TECHNICAL SKILLS:

Languages : VHDL, Verilog HDL, C, Assembly languages of 8086/8051.

EDA Tools : Cadence-Virtuoso, Xilinx-ISE, Chip Scope-Pro, Model Sim, Keil μ vision.

Hardware : Virtex-5, Spartan-3E FPGA board.

Course work : Basics of VLSI, Digital System Design, VLSI System Design, Testing &

Verification of VLSI Circuits and Embedded System Design.

M.TECH MAJOR PROJECT:

AN IMPROVED LDPC SPLIT ROW DECODING ALGORITHM:

Aim of the project is to detect the error correction and detection is possible at decoding side

using error correcting code namely low density parity check code (LDPC). The work is considered

in matrix form which is a sparse matrix here the data is checked by using rows and columns where

the process is completely updated for every single row and column .By assuming an data at the

encoded side and that data has to be exactly decoded, if any misplacement of data has been taken

place it automatically detects and corrects. But by doing so for a large matrix it becomes very

complex. So now the matrix is divided in to two parts where the complexity is reduced by half and

it is easier one to compute now again if any unused data is present then it has to be discarded by

providing a threshold value then it just compares the partition values in each matrix such that it

becomes more easier to discard unwanted data and finally decode data has been generated.

Tool: XILINX ISE12.1

INTERN PROJECT AT NARL:

DEVELOPMENT OF ELECTRIC FIELD MILL:

The relative change of electric field in atmosphere is estimated by using an instrument

named as electric field mill. The sensed signal is grounded, from there onwards it is provided to

charge amplifier and different amplifying stages finally calculating the electric field.

ROLE AND RESPONSIBILITIES:

1. The schematic circuit is developed using Orcad capture & layout.

PCB board for the schematic is developed and the grounded signal is given to first stage

2.

amplifier and respective amplifying stages and tested the board.

Tool: CADENCE ORCAD

M.TECH MINI PROJECTS:

• Delay analysis of a logic circuit with and without logical efforts.

Tool: CADENCE VIRTUOSO

• Development of audio codec on Xilinx Spartan-3E FPGA.

Tool: XILINX ISE12.1

• Designing a double Edge Triggered Flip-Flop using clocked inverter logic.

Tool: XILINX ISE12.1

B.TECH PROJECTS:

• EFFICIENT

IMPLEMENTATION OF CONVOLUTION ON FPGA: This project implements the

convolution of two discrete sequences on FPGA using VHDL. Compared to DSP computations,

high level FPGA implementation of convolution using VHDL has better speed performance,

power consumption.

• CONTINOUS INDOOR

NAVIGATION WITH RFID: This project has mainly RFID cards will be attached in a room.

An RFID reader will be in our hands. We will carry the reader with us by passing through the

cards it will display room details on LCD which will be helpful for dump people and sound

recorder which provides sound details of the room for blind people.

DECLARATION:

I hereby declare that the above furnished information is true to the best of my knowledge.

Date:

S.ABDUL SAJID

Place:

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