Abhishek Kumar Singh

***, ***** **** *****, ***** Garden, Marthahalli, Bangalore 560037

+91-810-******* • aco0lz@r.postjobfree.com

Summary

Professional

* ***** ** ***** ** experience in physical implementation & STA.

Experience in different aspects of backend design which includes: floor planning, power planning,

placement optimization, clock tree structure, routing, parasitic extraction, signal integrity analysis

and repair, ECO, Physical Verification.

Experience of multiple voltage domain designs involving low power methodology implementation.

Last 2 years involved in physical implementation & STA of high-speed ARM core CPU and GPU

Experience in various PnR & Signoff tools like : EDI, ICC, Talus, Primetime

WORK EXPERIENCE

Qualcomm, Bangalore, India

4/2013 - current

Engineer, Physical Implementation & STA

Have worked on 3CPU & 1 GPU designs; having ARM cores & frequency in excess of 1GHz.

Have worked on all aspects of physical implementation including: floorplanning, placement, clock

distribution, routing, signal integrity.

Have worked on many studies involving choice of synthesis tool with PnR tool

On STA side: complete ownership of STA setup. Have worked on debugging the constraints,

running STA & providing feedback to block owners, analysis of complex paths & create timing

ECOs

Have worked on multiple feasibility experiments for power (leakage & dynamic) reduction in both

physical implementation & STA.

Synopsys, Bangalore, India

4/2011-3/2013

Application Engineer

Supported Talus & ICC to its major customers in the region. Have worked on issues ranging from

library setup to routing & design closure.

Good knowledge of internal work-flow and ‘recommended methodology’ of these tools.

Have been part of various evaluations & benchmark for Talus.

Worked closely with design teams in crunch time and led them to successful tape-out.

Active involvement in giving regular trainings to clients and mentoring new joiners

Wipro, Bangalore, India 6/2010-3/2011

Project Engineer

Physical Implementation of Digital block was done starting form library setup till DRC cleanup &

physical verification. Implementation was done using soc encounter.

Professional Training

ICC, Primetime, Design Complier, Verilog, Static Timing Analysis

EDUCATION

Indian School of Mines, Dhanbad, India 5/2010

Bachelor of Technology, Electrical Engineering

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