Design Engineer

Gopal Takale

• **** Iron Point Rd #****, Folsom, CA, 95630 •916-***-**** •***********@*****.***

OBJECTIVE: Seeking a full time position involving digital logic design/ verification/ validation/ testing in ASIC/FPGA

design and computer architecture.

EDUCATION: MS (Computer Engineering) • CSU Sacramento, CA • GPA 3.6 • August 2012- Dec 2014

• Pune University, India • GPA 3.5 • August 2007- July 2011

BE (Computer Science)

COURSEWORK:

• Digital IC Design • Hierarchical Digital Design Methodology • Digital Electronics and Logic Design

• Operating System • Computer System Structure • Comp Aided Sys Design Verification

• Computer Network • Micro-Computer System Design • Advanced Computer Architecture

• Distributed Systems • Data Structures and Algorithms • Object Oriented Programming

KNOWLEDGE AND SKILLS:

• Languages: •Verilog •System verilog •VHDL •C •C++ •Perl •TCL •Java Script

• EDA Tools: •Synopsys VCS •Pspice •Design Vision •L-Edit v7.12 •Pspice •Triage • Verdi •Prime Time

• Skills: •Intel IA 32 Architecture •PCI protocol •RTL design, verification and validation •Timing analysis

•Simulation •Code and Functional Coverage •CMOS •VLSI.

WORK EXPERIENCE:

Pre-silicon Validation Intern, Intel Corporation, Folsom CA March 14- August 14

Front end validation and test generation of Fetch and Decode unit in Intel’s big core team.

Modifying test environment, random templates and Perl libraries for random instruction generation.

Basic test runs for all feature integrations and debug all long running tests.

Adding more templates while guaranteeing fast turnaround time.

Propose modifications to test templates to hit corner cases and to detect bogus branch related to BPU.

Add checker for given scenarios to detect test failure with a particular bug.

PROJECTS:

Digital IC design and CMOS Layout: Fall '12

Designed a 3-bit serial adder with accumulator and optimized gate level design using Synopsys VCS tool. Built a

transistor level circuit for optimized gate level design and simulated it in Pspice to verify the functionality. Also ESD

protection circuits were designed for the inputs. Finally, chip was layout using the 0.5um CMOS technology in L -Edit

v7.12 and for physical verification a DRC test was run to eliminate errors.

Datapath for Pipelined MIPS Instruction set: Fall '12

Designed and simulated a datapath in Verilog for a pipelined system. It executed MIPS instructions like add.s, sub.s, lwcl,

swcl, c.eq.s, bclt etc. Top module was developed to check functionality of overall integrated datapath. Implemented

forwarding unit to handle data hazards.

Pipelined floating point multiplier: Spring '13

Design, simulation and synthesis of pipelined Floating Point multiplier. The design was modeled using Verilog, developed

test bench to validate and synthesized in Synopsys Design Compiler. TCL script was written to generate area and timing

report and to get least time slack possible. Project aimed to improve code coverage and reduce timing and area.

DMA Client & Arbiter design: Spring '13

Designed a DMA with 6 clients and an arbiter in System Verilog and simulated in Synopsys VCS. Clients are given grant

by arbiter according to round robin fashion and they can write and read which is based on their preference to access the

bus. System is automated using program. Added constrain and functional coverage (bins) for randomized inputs.

PCI target design: Fall '13

Designed a 32 bit Target PCI Memory which supports linear addressing mode and executes commands like Memory

write, Memory Read, Memory Read Line and Memory Write Invalidate. Supports latency modes such as Target abort,

Disconnect and Retry.

Static timing analysis: Fall '13

Designed an ALU using Verilog and tested it using Perl scripts. Optimized a given netlist and generated area & timing

reports in Design Vision and performed checks for hold and setup slack. Analyze the design by writing TCL scripts with

constraints.

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