Design Project

Xudong Bai

Email: *******.*******@*****.*** Phone: 213-***-**** Address: 1596 Sonoma Dr, Milpitas, CA 95035

OBJECTIVE:

Seeking a full-time or intern position in the areas of ASIC design, RTL design or verification.

SUMMARY:

Recent MSEE graduate specializing in ASIC design and verification. Hands on experience in RTL design and

completed many industrial level projects such as DDR2 controller and Tomasulo CPU. A dedicated person with

good project management skills. The general purpose CPU project, using unique structures and optimization,

won top 1 design among 60+ groups in the class. Achieved another top 1 design of Asynchronous NoC with

Forward Error Correction through hard working and attention to details.

EDUCATION: MSEE at University of Southern California, Los Angeles, CA GPA: 3.5 May 2014

BSEE at University of Engineering Science, Shanghai, China GPA: 3.5 June 2012

Exchange student at Halmstad University, Halmstad, Sweden GPA: 3.7 Jan 2011

COURSE WORKS & SKILLS:

• Programming Languages: Verilog RTL, C++, Java, VHDL, Python, System Verilog, UVM.

• Computer Architecture: Computer Systems Architecture,Computer Systems Organization

• Analysis of Algorithms

Algorithm:

ACADEMIC PROJECTS:

DDR2 SDRAM Controller (Verilog, Cadence NC-Sim, Synopsys Design Compiler)

• Designed a DDR2 controller to perform scalar and block read/write with clock cycle of 2ns

• Synthesized with Synopsys DC using 45nm technology and Simulated with Denali DDR2 model

• Simulated the design with Denali DDR2 model

Tomasulo Out-of-Order Processor (MIPS CPU, VHDL)

• Built Tomasulo CPU to schedule and execute MIPS instructions out-of-order

• Performed RTL design of Issue Queue, CFC, FRL, BPB, ROB, FIFO and priority search resolver

• Synthesized the design and verified it on Spartan-3E FPGA using Xilinx ISE

General Purpose Mmulti-cycle CPU with 1K SRAM (Cadence Virtuoso) [Top 1 among 60+ teams]

• Developed a full custom general purpose multi-cycle CPU to support LW/SW, add, multiply instructions

• Implemented 1K-bit 2 dimensional SRAM block, an area optimized 16-bit multiplier and a 16-bit CLA

• Achieved the smallest area*delay product among all teams using well organized structures

Asynchronous NoC with Forward Error Correction (System Verilog, Proteus) [Top 1 of 20+ teams]

• Designed 3 asynchronous NoC (Network-on-Chip) with different topologies and packet switching

• Built hamming code error detection/correction to encrypt, decipher and correct data.

• Synthesized all the basic blocks using Proteus except arbiter and implemented the design in gate level

ASIC Verification Using UVM (System Verilog, Modelsim)

• Verified a simple FIFO and a vending machine with constraint random coverage driven methodology

• Created UVM environment including driver, sequencer, sequence, monitor and scoreboard

Translate a Verilog design into OOP design (C++, Linux, Gdb)

• Parsed a FLEX(verilog.lex) file in, then created object models using the class definitions

• Modeled components using inheritance and polymorphism concepts

• Used the STL map class to quickly index other objects, Performed topological sort/DFA search algorithms

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