KIRANKUMAR MAHANTHI

#***/**,

N.G.R Complex,

Bannergatta main road,

Arekere gate, Email:

acn9ex@r.postjobfree.com

Bangalore -560076. Mobile:

+919********* / +919*********

__

Career Objective:

Intend to build a career with leading corporate of hi-tech environment

with committed and dedicated people, which will help me to explore myself.

Summary of Qualifications:

> Good understanding of the ASIC and FPGA design flow.

> Experience in writing RTL models in Verilog HDL and Test benches in

System Verilog.

> Good knowledge in Verification Methodology using System Verilog and

UVM.

> Experience in using industry standard EDA tools for the front-end

design and verification.

Technical Skills:

Languages : C, Perl.

HDLs : Verilog and VHDL.

HVL & TB Methodology : System Verilog and UVM.

Verification Methodologies : Coverage Driven Verification, Assertion Based

Verification.

Domain : ASIC/FPGA Design Flow, Digital Design

methodologies.

EDA Tools : Questa-sim & Xilinx ISE (for RTL

Design, simulation & synthesis)

Knowledge: RTL Coding, FSM based design, CMOS,

Code Coverage, Functional

Coverage,

Static Timing Analysis,

ABV, OOPs.

Professional Qualification:

July to Nov 2013 Certified course on Advanced VLSI Design And

Verification

From: Maven Silicon VLSI Design & Training Center,

Bangalore.

2009 to 2013 Bachelor Of Technology in Electronics &

Communication Engineering

COLLEGE: Sri Venkateshwara Institute of Science &

Information Technology,

Tadepalligudem.

Percentage: 65.03

2007 to 2009 Board Of Intermediate Education (M.P.C)

COLLEGE: Aditya Junior College, Tadepalligudem.

Percentage: 79.90

2006 to 2007 SSC

SCHOOL NAME: Gurajada Vidya Nikethan,

Tadepalligudem.

Percentage: 73.33

Achievements:

> Participated in paper presentation conducted in BVC Engineering

College at Amalapuram, Andhrapradesh.

> Participated in technical quiz and circuit designing held at Gayathri

College of Engineering at Visakhapatnam, Andhrapradesh.

> Participated in paper presentation on "DIGITAL AUDIO BROADCASTING"

and short film held at Sri VISIT Engineering College at

Tadepalligudem, Andhrapradesh.

Personal Skills:

. Positive Attitude.

. Team Facilitator.

. Good at achieving tough tasks & High motivation.

VLSI Projects:

TITLE: VIDEO GRAPHICS ADAPTOR - RTL DESIGN

HDL: Verilog

EDA Tools: Modelsim, Questa - Verification Platform and ISE

> Architected the design

> Implemented the RTL using Verilog HDL

> Verified the RTL using Verilog HDL

> Implemented the design on the Spartan, Xilinx FPGA and verified the

design on the board

TITLE: DUAL PORT RAM - VERIFICATION

HVL: System Verilog

EDA Tools: Modelsim, Questa - Verification Platform and ISE

> Implemented the Dual Port Ram using Verilog HDL independently

> Architected the class based verification environment using system

Verilog

> Verified the RTL module using System Verilog

> Generated functional and code coverage for the RTL verification sign-

off

TITLE: ROUTER 1X3 - RTL DESIGN AND VERIFICATION

HDL: Verilog

HVL: Systemverilog

EDA Tools: Modelsim, Questa - Verification Platform and ISE

Description:

The router accepts data packets on a single 8-bit port called data

and routes the packets to one of the three output channels, channel0,

channel1 and channel2.

> Architected the design and described the functionality using Verilog

HDL.

> Architected the class based verification environment using system

Verilog

> Verified the RTL model using Systemverilog.

> Generated functional and code coverage for the RTL verification sign-

off

> Synthesized the design.

Engineering Project:

TITLE: CYCLIC REDUNDANCY CHECK USING MULTIPLE LUT ALGORITHMS

HDL: Verilog

EDA Tools: Modelsim, Xilinx ISE

Description:

Slicing by 8 algorithm is designed and compares this algorithm with

existing algorithms like sarwate algorithm and LFSR method. Slicing by-N

algorithm can read arbitrarily large amount of data at a time and reduces

time requirement. So this method is applied to CRC generator with slicing

by-N algorithm will be proposed in ISCSI (internet small computer system

interface).

Personal Details:

Father's name : M. Pedda Appala Naidu

Date of Birth : 17-08-1992

Gender : Male

Marital Status : Single

Nationality : Indian

Languages Known : Telugu, English.

Hobbies : Listening to

music, Playing cricket.

Declaration:

I hereby declare that the above stated information is true up to the

best of my knowledge and I bear the responsibility for the correctness of

the above-mentioned particulars.

(KIRANKUMAR MAHANTHI)

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