VLSI Design Engineer
Resume:
RAMANAN RAJENDRAN RAJAMANI
PONDICHERRY.
*******.****@*****.***
EXPERIENCE SUMMARY:
Currently working as a VLSI Design Engineer for almost a year in ONE POINTER
TECHNOLOGY, Pondicherry from April-2014 to till date.
EXPERTISE SUMMARY:
Almost a year of experience in VLSI Domain.
Designing and developing circuits based on client's requirement.
Direct interaction with clients to know about thier requirement.
Technical support and assistance to clients.
Hands on experience in using CADENCE.
Currently working in Analog Design domain of our company, using CADENCE-IC616 90nm
technology.
Working knowledge in CADENCE-VIRTUSO-IC616 ADE and ADE-L environment.
Also trained in Digital designing using XILINX 14.7 and XILINX VIVADO.
Done few projects using XILINX 14.7 and SPARTAN 6.
EDUCATION PROFILE:
September 2012 – January 2014: Master of Engineering in VLSI Systems (Ireland).
Institute : University of Limerick, Ireland.
Result : Grade-1 Honours.
Summary:
University of Limerick is one of the world's top 100 youngest universities.
Awarded Faculty of Science and Engineering Scholarship by University of Limerick.
Attended MIDAS(Microelectronics Industrial Design Association)-Ireland IC Design Fest at
Dublin City University, Dublin over a week.
Visited Intel Fab 24 – Fabrication unit as guest visitor at Leixlip, Ireland.
Assisted one of my professors in developing a project apart from my final thesis.
August'08-June'12 : Bachelor of Engineering in Electronics and Communication.
Institute : Meenakshi Sundararajan Engineering College (Anna University), Chennai.
Result : First Class
Summary:
Final year project internship at NIELIT(National Institute of Electronics and IT), Chennai.
Coordinator of ’PRANAV-11’, a National Level Technical Symposium conducted by the
Electronics and Communication department of our College.
Member of Documentation Committee of our College’s Electronic and Communication
Department News letter WIRED.
Participated in Academic Developer Conference’11, Microsoft DreamSpark Yatra at SRM
University, Chennai.
Attended workshops and inplant trainings during my tenure in the college.
PUBLICATION:
Concern : National Conference on VLSI and Image Processing - 2012, Chennai.
Title : ASIC Design of Two novel 8 Transistors Full Adder Cells using Cadence 180nm, 90nm and
45nm.
INTERNSHIP – Final Year Project (November'11- March'12):
• Final Year Project (B.E) Internship at NIELIT (National Institute of Electronics and IT), Chennai,
under Government of India.
• Worked on Cadence GPDK 180nm, 90nm and 45nm Technologies.
• Designed 2 new novel full adder designs in ASIC using only 8 transistors.
• Our design resulted in better Area, Power and Delay when compared with 10 other designs. The
Layout of the designs were also carried out successfully.
• Our design was published at a National Conference in Chennai.
• Trained in Verilog, VHDL, SPARTAN 6 and Chip Scope Pro.
TECHNICAL SKILLS:
Cadence-Virtuso-IC616:
• Cadence Virtuso with technologies including AMS 0.35µ,AMS 0.18 µ and GPDK 180nm, 90nm
and 45nm.
• Cadence Spectre Tools including ADE, Tran analysis, Gain, Noise, AC Analysis and DC
Analysis.
• Cadence Assura Tools including Layout Editor, DRC, LVS, Post layout simulation and
Extracting R and C parameters.
Xilinx 14.7:
• Knowledge of both Verilog and VHDL modules using Xilinx 14.7.
• Hardware Board Knowledge: SPARTAN 6, SPARTAN 3, ALTERA Cyclone IV.
MATLAB r2014a:
Have hands on experience in using MATLAB for Signal Processing, Image Processing and Digital
Controls.
C, C++,Shell Scripting, Python:
An advanced user of C,C++ since my Bachelor’s and a beginner in Shell Scripting, Java and Python.
ACADEMIC PROJECTS AND THESIS:
Design of 0.35µ Analog CMOS Amplifier for Biometric Sensing Application- MEng 2014
Achieving low noise in an amplifier is challenging, since critical EEG, EMG and ECG signals are
•
often found at low frequencies, leaving instrumentation susceptible to 1/f noise.
In this project, a CMOS amplifier using AMS 0.35µ was designed which is immune to 1/f noise
•
and consumes less power for EEG analog front end implementation for low power biosensor
enabling technologies.
The design achieved high gain, high CMRR, low power and also low noise.
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Design of Flexray Communication Controller for FPGA based Automotive Systems:
Modern vehicles incorporate an increasing number of distributed compute nodes, resulting in the
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need for faster and more reliable in-vehicle networks.
Time-triggered protocols like FlexRay have been gaining ground as the standard for high-speed
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reliable communication in the automotive industry, marking a shift away from the event-triggered
medium access used in Controller Area Networks (CAN).
I helped one of my professors in this project during my academic year. The project was developed
•
in verilog module and implemented using SPARTAN 6.
Analog ASIC Design and Implementation of Two Novel 8 Transistors Full Adders-B.E 2012:
• Full Adders are the basic building blocks of any adder, multiplier and processors.
• Hence two new full adders are designed using Cadence GPDK 180nm, 90nm and 45nm
technologies and the layout of them were also done. Our design achieved better performance in
terms of Area, Power and Delay.
Contact this candidate