Engineer

KARTHIKEYAN DAYALAN

Phone: 213-***-**** ** Walnut Street, Binghamton, NY 13905 ********@**********.***

EDUCATION

State University of New York at Binghamton Expected May 2015

Master of Science in Computer Science GPA: 3.40 / 4.00

Panimalar Engineering College, Anna University, Chennai, India May 2011

Bachelor of Engineering in Electronics and Communication Grade: 83 / 100

SKILLS

Programming Languages : C/C++, Java, COBOL, JCL, Verilog, SQL

Web Technologies : HTML, CSS, JavaScript

Tools : Simple Scalar (Cycle accurate Processor simulator), CACTI (Power & timing model), Valgrind

(Memory Mismanagement detector), Change man (version control), BMS, Cygwin

Operating Systems : Linux, Windows

PEER-REVIEWED PUBLICATIONS

Karthikeyan Dayalan, Meltem Ozsoy and Dmitry Ponomarev; “Dynamic Associative Caches: Reducing Dynamic Energy

of First Level Caches”;The 32nd IEEE International Conference on Computer Design (ICCD’14), Seoul, Korea. October 2014

WORK EXPERIENCE

January 2014 – Present

Research Assistant, Binghamton University

Proposed DAC(Dynamic Associative Caches) - the power efficient first level data cache design with less performance loss

and less complexity (Paper accepted to ICCD’14)

Implemented DAC within the processor simulator and analyzed its timing and power implications

Saved 85% of the dynamic energy with less than 1% performance loss.

June 2011 – July 2013

Systems Engineer, Infosys Limited, India

Maintained a section of supply chain processes in Leading Automobile company: Logistics Systems

Held responsible for Back-end productive job run and solved the abends with procedural techniques in Mainframes

Assigned tasks to a team of four people on daily basis with priority to solve them

Documented and updated all the abends and the Logistics Systems process for future use.

PROJECTS

February 2014 – May 2014

Ray Tracing

Simulated the path of light rays that would take from light source to the eye using GPU, CPU and smartphone.

GPU will process the image pixel by pixel, CPU will receive the input from smartphone and send it to GPU and vice versa

Implemented the CPU part in Cilk, GPU part by CUDA and the smartphone part by Android.

September 2013 – December 2013

Handling Long-latency Loads in Simultaneous Multi-Threading processor

Improved the performance by identifying the long latency loads and flushing them from the processor pipeline

Modified the simulator (M-sim) of more than 5000 lines of code to implement the above mechanism using C++

Implemented three new different methods for identifying the loads and compared it with current existing method

December 2010 – May 2011

Memory Based Realization of FIR Digital Filter

Designed a Digital Finite Impulse Response filter with new approach to Look-Up-Table Design using VLSI

technology and improved its memory efficiency

Implemented the design in Verilog code using Xilinx simulator to get the desired results

ACHIEVEMENTS

A first author of an IEEE paper “Dynamic Associative Caches” in ICCD’14 conference

Assigned as “Student Manager” in SODEXO to schedule and manage the timings for the events and the employees.

Graded as one of the best project in PROJECT EXPO- 2011, Department of CSE, IT & MCA in collaboration

with CSI (Computer Society of India)

Top 1% C developer in Codeeval Programming Challenges among 5000 competitors.

ACTIVITIES

Co-curricular

Presented paper in National Conference, NAVICS’11, Einstein College of Engineering, Tirunelveli

Organized Symposiums, AMBITUS’09 & NOUVEAUS’11 held at Panimalar Engineering College, Chennai

Extra-curricular

Conducted Counseling for low-income people about their health care and education, Velachery, Chennai

Taught Basics of Computer to low-income children through INFOSYS-SHIKSHA and managed a class of 40 students

Active Member of INFOSYS-SNEHAM, a foundation to help low-income families

Contact this candidate