Engineer Design

Albert Monera ******.******@*****.*** /+63-927-***-****

Summary I'm highly skilled in electrical fault isolation and debug of

Xilinx FPGA devices. I utilize my experience in circuit

schematic/layout analysis, bench system setup/testing, DFT's, ATE

testing (BIST/SCAN) and datalog analysis, global isolation tools,

etc to be efficient and successful in my work. I have good rapport

with Design Engineers, Product Engineers, Quality and Reliability

Engineers as I work with them to find solution to device quality

issues I uncover as a result of my work. I help my management keep

track of metrics by maintaining, generating and analysing pivot

reports quarterly. I currently manage and perform internal device

debug requests from device qualification and production.

Experience Staff Fault Isolation Engineer (Product Quality Engineering) @

Xilinx Singapore from 2008 to 2015

Works on FPGA devices with focus on High Speed Serial IO (Xilinx

Gigabit Transceivers). Currently preparing readiness for support

ARM SoC with focus on Structural Test Diagnostics using Mentor

Tessent

Perform debug on customer returns by studying their failure modes,

field application reports, supplied Verilog design/schematics then

create simplified test cases to correlate customer issue using ISE

and Vivado.

Supports Internal Engineering Debug requests from mature devices to

latest Xilinx 7 Series Products (FPGAs, ARM SoC+FPGA)

Supports debug of PROM RMA, bench testing using Nextest Maverick

I/II

Very familiar with lab tools including but not limited to Agilent

MSOX90K, Keithley 2400 SourceMeasure, Tabletop Osciloscopes,

Temptronics Force Temperature

Recipient of two Recognition awards and first ever Quality

Leadership Award 1H2012

Fault Isolation and Failure Analysis Engineer @ Intel Philippines

from 2003 to 2007

Divisional FI/FA Lead in three New Product Cycles (Enterprise

Chipsets - Northbridge)

Created and Successfully Executed Project Plan to be able to

provide FI/FA support adequately for New Products - planned

cost/delivery of collaterals such as FI test load boards, Debug

Test Patterns and knowledge transfer from Division to Factory

Performed Latch-Up Stress Testing on New Products to meet JEDEC

specifications

Perform architecture and die level fault isolation and

characterization to root-cause failure analysis on latest

generation IC products

Report and Document Root Cause Analysis to Product Development Team

Created scripts/programs in Linux/Unix

Design Engineer@ ROHM LSI Design Philippines from 2001 to 2003

Mask Layout Department

Designed Physical Mask Layout based on circuit schematic

requirements and indications in the shortest amount time in the

training batch

Verify, Simulate and Characterize Digital Cells and compile into

Standard Cell Libraries

Schematic Design Entry using Cadence Virtuoso

Analog/Digital circuit design, schematic entry and simulation on

reversed engineered layout patterns

Created automation scripts/programs using awk and command line

scripts

B.S. Electronics and Communications Eng'g @University of the

Education Philippines in 2000

High marks in 6 units of embedded design theory and lab using Zilog

Z8 Microcontroller which includes machine code programming and

component assembly on bread board.

FPGA, PROM, Bench/AppsTesting, Scopes, Sig Gens, Xilinx ISE/Vivado,

Skills Windows OS, UNIX & LINUX Environment/shell scripting, Verilog,

System Verilog, Xilinx ISE, ATE,FIB,SEM, IREM, OBIRCH, Load Board

Design, DFTs and Test Methodologies, High Speed Serial I/Os, 8D

Report,DOE,JMP, MRB, CAR, RMA, JEDEC, ESD, Latch-up Stress, JTAG,

TI-Fusion, Project Mgmt Fundamentals

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