Analog Design

SUNDARAIAH GURINDAGUNTA

PRESENT ADDRESS: DATE OF BIRTH: 14-APRIL-1986

MARATHAHALLI, MOBILE: +91-944*******

E M A I L : ***********@*****.***/ @yahoo.co.in

BANGALORE, KA-560037

Objective

Seeking a challenging position in Analog/Mixed signal domain that will enable me to use my strong

organizational skills, educational background and ability to work well with people through hard

work

Education Details

M.Tech in Microelectronics and VLSI Design at IIT Madras (2010-2012)

CGPA: 8.17/10

B.Tech in Electronics and Communication (Lateral Entry) at LBRCE, Mylavaram, Vijayawada,

Andhra Pradesh, India (2004-2007)

Percentage: 72.89%

Diploma in Electronics and Communication Engineering at DRBRAGMR Polytechnic,

Rajahmundry, Andhra Pradesh, India (2001-2004)

Percentage: 79.19%

SSC at SPNRC High School, Vijayawada, Andhra Pradesh, India (2001)

Percentage: 80.16%

Professional Experience

Analog Design Engineer - II

Marvell Asia Private Limited, Singapore (July2012–Jan2015)

Working in the Power Management group of the company and responsible for the Circuit

o

Design, Layout supervision of various Analog blocks, FPGA verification, IC Evaluation and

Customer Support for Single/Three Phase Fan Motor Controllers

Design:

Voltage and Current References

Linear Regulators with both Voltage and Current Mirror OTA

- 5-18V i/p - 5V o/p LDO, 30mA Load Current

- Bit Selectable o/p voltage with fixed no load current, 0~30mA & 0~20nF Load

- Shunt Regulator

- Supply to o/p voltage difference Open Loop Regulator to sink switching currents

8/10-bit programmable SAR ADC with incorporated Current Steering DAC

Oscillator with Process, Voltage and Temperature compensated

PLL/DLL in 0.13um technology

Master Reset to provide digital reset and UV to provide start signal upon power up

Voltage and Current based Comparators with well controlled and programmable

hysteresis/offset

3-phase motor external FET Driver supporting blocks (Confidential)

Bench:

Work with Digital team to verify the proposed algorithms on FPGA

Evaluation and characterization of designed blocks and algorithms after tape-out

Customer evolution according to their specs

Assistant Professor

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Sri Saradhi Institute of Engineering and Technology, India (Nov2008–May2010)

Sai Spurthi Institute of Technology, India (Jun2007–Nov2008)

Responsible to:

o Instruct, guide and mentor students in their academic subjects, Labs and projects

o Develop, innovate and implement innovative instructional methods and career -

enhancement programs and activities

o Assess, review and evaluate student activities and progress

o Participate, serve and support the departmental and college functional activities

Areas taught: Digital Design, Control Theory, Computer Organization, Verilog/VHDL,

Pulse Circuits, Signals and Systems

Practical works: Pulse and Digital Circuits Lab, Analog Communication Lab, Electronic

CAD Lab, Micro Processors Lab and Electronic Circuits Lab

Academics

M.Tech Course Work:

Analog IC Design VLSI Data Conversion Circuits

Semiconductor Device Modeling Digital IC Design (Basic/Advanced)

VLSI Technology Digital Signal Processing

M.Tech Project:

Adder Designs in Carbon Nanotube Field Effect Transistor Technology

Abstract: As Silicon technology reaches its end we have to look for new material which will

fit with silicon technology or even to substitute the entire technology. There is plenty of

room at bottom. Among them CNTFET is at top because of its unique properties and has

the capable of replacing entire Si -Technology. The CMOS circuits realized in Si -Technology

can be realized in CNTFET too without any changes in structure.

Since, the threshold voltage of CNTFET can vary by simply diameter, this project mainly on

implementing multi-level logic circuits in multi threshold logic

In this project, only ternary logic was taken to implement, but we can extend these

methods (ideas) to higher radix circuits as well

Proposed a method to get the output quickly when the output is cascading for low power

ternary circuits and designed multi-trit adders with this method to show there is large

saving in power delay product

Carry look-ahead adder in ternary which resembles binary CLA. The circuit judges any level

of CLA can be realized in mirror structure

Part of work get published in IEEE transactions on Nanotechnology titled “Efficient Multi-

Ternary Digital Adder Design in CNTFET Technology” (10.1109/TNANO.2013.2251350 )

Technical skills

Operating Systems : Microsoft Windows, Ubuntu, UNIX

Software Languages : C, C++, Assembly Language, LATEX

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HDL : VHDL, Verilog

Software Skills : MATLAB, Scilab, HSPICE, ELDO SPICE, TSPICE, SmartSPICE, ECS,

Xilinx, Modelsim, Cadence, KBDD, Laker, Discovery-AMS

Personal Profile

Parents : Raghavamma and SubbaRao

Nationality : Indian

Languages : Telugu and English

Permanent Address : #9-89, Gollapudi, Vijayawada, Andhra Pradesh, India-521225

Reference

Ravishanker Krishnamoorthy

Design Director,

Marvell Semiconductors,

Singapore.

Mobile: +65-97330593

Email: ********@*****.***

Declaration

I hereby declare that all the details furnished above are true to the best of my knowledge and

belief.

[Sundaraiah G]

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