Project Design

NAVATHEJ N BANGARI

Mobile Phone: 996-***-****

E-mail:********.*******@*****.***

Looking for a challenging position as an ASIC design/verification engineer where I can learn

and grow.

Summary of Qualifications

• Strong Digital Design Skills

• Expertise in FPGA design /RTL design flow with fluency in HDL coding.

• Good understanding of System Verilog, latest verification methodology UVM and

System Verilog Assertion.

• Knowledge of Constrained-Random test cases, Coverage Driven verification.

• Knowledge on how to develop Driver, Generator, Monitor and Scoreboard using

system Verilog.

Professional Experience Sion Semiconductors pvt lmt (12+ months), Bangalore

Project Trainee

Academic Qualification

YEAR OF

DEGREE SCHOOL/COLLEGE UNIVERSITY Percentage

PASSING

M.Tech

VLSI Design and RNSIT 75

2014 VTU

Embedded Bangalore

systems

GMIT

2012

B.E Davangere VTU 74

KODIMATA PU

PUC College 81.16

2008 KEA Board

Arsikere

Adhichunchanagiri

SSLC school Arsikere. 2006 KEA Board. 85.28

Certifications

Verification Using System Verilog by Sion Semiconductors. Aug 2014

Universal Verification Methadology by Sion Semiconductors Oct 2014

Technical Expertise

• HDL's: Verilog, System Verilog

• Simulators: ModelSim, QuestaSim

• Application Tools : Xilinx, Cadence.

• Verification Methodology: UVM

• Bus Protocol: I2C, SPI, AMBA(AHB,APB)

PROJECTS

PROJECT 1: VERIFICATION OF AMBA APB BUS

Description: To prepare a class based layered test bench environment in UVM to verify APB

WRITE and READ TRANSFER.

Responsibility:

• Understood the AMBA APB Protocol.

• Planned the Verification Architecture.

• UVM Based Environment.

• Implemented Test cases for verification of IP

• Developed coverage model and Scoreboard for the IP.

• Features Verified.

a) Single read and write

b) Multiple write at a time then multiple read at those addresses

c) Reading in unwritten address

d) Reading or writing outside of "read-write address" range (9MB - 18MB)

PROJECT 2: Memory Controller

Description:To prepare a class based layered test bench environment in SystemVerilog and

also in UVM to verify Memory for Read, Write and Reset operations.

Responsibility:

• All the parts of testbench (Transaction, Generator/Sequencer, BFM/Driver, Interface,

Monitor, Checker/Scoreboard, Agent and Environment) is developed in

SystemVerilog and also in UVM.

• Directed testcases and Constrained-random testcases are written to perform Write,

Read and Reset operations.

• Developed a Functional coverage model, hooked it in testbench and analyzed the

report.

PROJECT 3: FPGA IMPLEMENTATION OF LOW POWER PIPELINED 32-BIT

RISC PROCESSOR

Description: Here in this project I was successfully designed and implemented Low power

pipelined RISC Processor. The various blocks include the Fetch, Decode, Execute and

Memory Read / Write Back to implement 4 stage pipelining. And I also proposed low power

design technique in front end process.

Responsibility: Design of Instruction Fetch Unit, Instruction Decode Unit, Execution Unit,

Memory unit and Low power unit is done in Verilog. And also integration of the design and

simulation.

PROJECT 4: Ethernet for FPGA-PC communication

Description: This project was to design an interface that enabled the FPGA board to

communicate with other devices via the on-board Ethernet connection.

Responsibility: Design of 10 Base T Ethernet MAC has been done in verilog and

implemented the same on Spartan 3E FPGA Board.

Development/ Productivity Tools: Xilinx, Spartan 3E

PROJECT 5: Design and verification of Single Port and Dual Port RAM using system

verilog

Description: To prepare a class based layered test bench environment in SystemVerilog (SV)

to verify Memory for Read, Write and Reset operations in Single port and Dual Port RAM.

Responsibility: All the parts of testbench (Transaction, Generator/ Sequencer, BFM/Driver,

Interface, Monitor, Checker/ Scoreboard, Agent and Environment) is developed in

SystemVerilog. Directed testcases and Constrained-random testcases are written to perform

Write, Read and Reset operations.

PROJECT 6: INTELLIGENT GASEOUS FUEL LEAKAGE DETECTION WITH

ALERTING SYSTEM

Description: In this project gas sensor was used and was able to detect gases such as lpg,methane and other poisonous gases .As soon gas detected, the embedded system designed by

us was able to turn on the exhaust fan and also it send messages to the authorized person

using GSM model.

Development/ Productivity Tools: PIC Microcontroller, GSM

OTHER ACTIVITIES:

• Reading Books

• Acted in many mad adds

• Playing shuttle and chess

PERSONAL TRAITS:

• Goal Oriented

• Dynamic & Hardworking

• Good in Team Work

• Good in Inter personal relationship and communications

• Willingness to learn and grow

DECLARATION:

I do hereby declare that the above-furnished information is true to the best of my knowledge.

DATE: (Navathej N Bangari)

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